Revision b7da58fd hw/ppc4xx_devs.c
b/hw/ppc4xx_devs.c | ||
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873 | 873 |
sdram_map_bcr(sdram); |
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} |
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} |
876 |
|
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/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. |
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* |
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* sdram_bank_sizes[] must be 0-terminated. |
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* |
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* The 4xx SDRAM controller supports a small number of banks, and each bank |
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* must be one of a small set of sizes. The number of banks and the supported |
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* sizes varies by SoC. */ |
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ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, |
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target_phys_addr_t ram_bases[], |
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target_phys_addr_t ram_sizes[], |
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const unsigned int sdram_bank_sizes[]) |
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{ |
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ram_addr_t ram_end = 0; |
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int i; |
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int j; |
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|
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for (i = 0; i < nr_banks; i++) { |
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for (j = 0; sdram_bank_sizes[j] != 0; j++) { |
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unsigned int bank_size = sdram_bank_sizes[j]; |
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|
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if (bank_size <= ram_size) { |
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ram_bases[i] = ram_end; |
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ram_sizes[i] = bank_size; |
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ram_end += bank_size; |
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ram_size -= bank_size; |
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break; |
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} |
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} |
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|
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if (!ram_size) { |
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/* No need to use the remaining banks. */ |
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break; |
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} |
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} |
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|
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if (ram_size) |
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printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n", |
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(int)(ram_end >> 20)); |
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return ram_end; |
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} |
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