root / hw / vmware_vga.c @ b80d4a98
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/*
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* QEMU VMware-SVGA "chipset".
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*
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* Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "loader.h" |
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#include "console.h" |
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#include "pci.h" |
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#include "vmware_vga.h" |
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#define VERBOSE
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#undef DIRECT_VRAM
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#define HW_RECT_ACCEL
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#define HW_FILL_ACCEL
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#define HW_MOUSE_ACCEL
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# include "vga_int.h" |
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struct vmsvga_state_s {
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VGACommonState vga; |
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int width;
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int height;
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int invalidated;
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int depth;
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int bypp;
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int enable;
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int config;
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struct {
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int id;
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int x;
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int y;
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int on;
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} cursor; |
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target_phys_addr_t vram_base; |
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int index;
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int scratch_size;
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uint32_t *scratch; |
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int new_width;
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int new_height;
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uint32_t guest; |
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uint32_t svgaid; |
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uint32_t wred; |
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uint32_t wgreen; |
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uint32_t wblue; |
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int syncing;
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int fb_size;
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ram_addr_t fifo_offset; |
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uint8_t *fifo_ptr; |
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unsigned int fifo_size; |
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target_phys_addr_t fifo_base; |
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union {
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uint32_t *fifo; |
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struct __attribute__((__packed__)) {
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uint32_t min; |
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uint32_t max; |
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uint32_t next_cmd; |
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uint32_t stop; |
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/* Add registers here when adding capabilities. */
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uint32_t fifo[0];
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} *cmd; |
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}; |
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#define REDRAW_FIFO_LEN 512 |
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struct vmsvga_rect_s {
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int x, y, w, h;
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} redraw_fifo[REDRAW_FIFO_LEN]; |
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int redraw_fifo_first, redraw_fifo_last;
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}; |
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struct pci_vmsvga_state_s {
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PCIDevice card; |
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struct vmsvga_state_s chip;
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}; |
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#define SVGA_MAGIC 0x900000UL |
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#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
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#define SVGA_ID_0 SVGA_MAKE_ID(0) |
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#define SVGA_ID_1 SVGA_MAKE_ID(1) |
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#define SVGA_ID_2 SVGA_MAKE_ID(2) |
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#define SVGA_LEGACY_BASE_PORT 0x4560 |
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#define SVGA_INDEX_PORT 0x0 |
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#define SVGA_VALUE_PORT 0x1 |
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#define SVGA_BIOS_PORT 0x2 |
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#define SVGA_VERSION_2
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#ifdef SVGA_VERSION_2
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# define SVGA_ID SVGA_ID_2
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 1 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_MEM_BASE 0xe0000000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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#else
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# define SVGA_ID SVGA_ID_1
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 4 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_MEM_BASE 0xe0000000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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#endif
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enum {
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/* ID 0, 1 and 2 registers */
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SVGA_REG_ID = 0,
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SVGA_REG_ENABLE = 1,
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SVGA_REG_WIDTH = 2,
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SVGA_REG_HEIGHT = 3,
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SVGA_REG_MAX_WIDTH = 4,
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SVGA_REG_MAX_HEIGHT = 5,
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SVGA_REG_DEPTH = 6,
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SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
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SVGA_REG_PSEUDOCOLOR = 8,
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SVGA_REG_RED_MASK = 9,
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SVGA_REG_GREEN_MASK = 10,
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SVGA_REG_BLUE_MASK = 11,
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SVGA_REG_BYTES_PER_LINE = 12,
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SVGA_REG_FB_START = 13,
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SVGA_REG_FB_OFFSET = 14,
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SVGA_REG_VRAM_SIZE = 15,
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SVGA_REG_FB_SIZE = 16,
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/* ID 1 and 2 registers */
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SVGA_REG_CAPABILITIES = 17,
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SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
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SVGA_REG_MEM_SIZE = 19,
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SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
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SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
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SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
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SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
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SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
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SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
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SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
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SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
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SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
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SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
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SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
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SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
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SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
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SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
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SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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}; |
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#define SVGA_CAP_NONE 0 |
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#define SVGA_CAP_RECT_FILL (1 << 0) |
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#define SVGA_CAP_RECT_COPY (1 << 1) |
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#define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
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#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
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#define SVGA_CAP_RASTER_OP (1 << 4) |
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#define SVGA_CAP_CURSOR (1 << 5) |
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#define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
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#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
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#define SVGA_CAP_8BIT_EMULATION (1 << 8) |
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#define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
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#define SVGA_CAP_GLYPH (1 << 10) |
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#define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
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#define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
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#define SVGA_CAP_ALPHA_BLEND (1 << 13) |
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#define SVGA_CAP_3D (1 << 14) |
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#define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
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#define SVGA_CAP_MULTIMON (1 << 16) |
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#define SVGA_CAP_PITCHLOCK (1 << 17) |
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/*
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* FIFO offsets (seen as an array of 32-bit words)
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*/
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enum {
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/*
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* The original defined FIFO offsets
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*/
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SVGA_FIFO_MIN = 0,
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SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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SVGA_FIFO_NEXT_CMD, |
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SVGA_FIFO_STOP, |
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/*
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* Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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*/
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SVGA_FIFO_CAPABILITIES = 4,
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SVGA_FIFO_FLAGS, |
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SVGA_FIFO_FENCE, |
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SVGA_FIFO_3D_HWVERSION, |
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SVGA_FIFO_PITCHLOCK, |
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}; |
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#define SVGA_FIFO_CAP_NONE 0 |
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#define SVGA_FIFO_CAP_FENCE (1 << 0) |
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#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
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#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
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#define SVGA_FIFO_FLAG_NONE 0 |
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#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
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/* These values can probably be changed arbitrarily. */
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#define SVGA_SCRATCH_SIZE 0x8000 |
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#define SVGA_MAX_WIDTH 2360 |
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#define SVGA_MAX_HEIGHT 1770 |
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#ifdef VERBOSE
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# define GUEST_OS_BASE 0x5001 |
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static const char *vmsvga_guest_id[] = { |
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[0x00] = "Dos", |
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[0x01] = "Windows 3.1", |
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[0x02] = "Windows 95", |
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[0x03] = "Windows 98", |
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[0x04] = "Windows ME", |
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[0x05] = "Windows NT", |
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[0x06] = "Windows 2000", |
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[0x07] = "Linux", |
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[0x08] = "OS/2", |
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[0x09] = "an unknown OS", |
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[0x0a] = "BSD", |
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[0x0b] = "Whistler", |
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[0x0c] = "an unknown OS", |
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[0x0d] = "an unknown OS", |
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[0x0e] = "an unknown OS", |
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[0x0f] = "an unknown OS", |
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[0x10] = "an unknown OS", |
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[0x11] = "an unknown OS", |
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[0x12] = "an unknown OS", |
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[0x13] = "an unknown OS", |
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[0x14] = "an unknown OS", |
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[0x15] = "Windows 2003", |
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}; |
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#endif
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enum {
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SVGA_CMD_INVALID_CMD = 0,
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SVGA_CMD_UPDATE = 1,
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SVGA_CMD_RECT_FILL = 2,
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SVGA_CMD_RECT_COPY = 3,
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SVGA_CMD_DEFINE_BITMAP = 4,
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SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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SVGA_CMD_DEFINE_PIXMAP = 6,
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SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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SVGA_CMD_RECT_BITMAP_FILL = 8,
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SVGA_CMD_RECT_PIXMAP_FILL = 9,
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SVGA_CMD_RECT_BITMAP_COPY = 10,
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SVGA_CMD_RECT_PIXMAP_COPY = 11,
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SVGA_CMD_FREE_OBJECT = 12,
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SVGA_CMD_RECT_ROP_FILL = 13,
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SVGA_CMD_RECT_ROP_COPY = 14,
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SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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SVGA_CMD_DEFINE_CURSOR = 19,
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SVGA_CMD_DISPLAY_CURSOR = 20,
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SVGA_CMD_MOVE_CURSOR = 21,
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SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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SVGA_CMD_DRAW_GLYPH = 23,
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SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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SVGA_CMD_UPDATE_VERBOSE = 25,
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SVGA_CMD_SURFACE_FILL = 26,
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SVGA_CMD_SURFACE_COPY = 27,
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SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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SVGA_CMD_FRONT_ROP_FILL = 29,
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SVGA_CMD_FENCE = 30,
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}; |
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/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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enum {
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SVGA_CURSOR_ON_HIDE = 0,
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SVGA_CURSOR_ON_SHOW = 1,
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SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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}; |
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static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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#ifndef DIRECT_VRAM
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int line;
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int bypl;
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int width;
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int start;
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uint8_t *src; |
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uint8_t *dst; |
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if (x + w > s->width) {
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fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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__FUNCTION__, x, w); |
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x = MIN(x, s->width); |
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w = s->width - x; |
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} |
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if (y + h > s->height) {
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fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
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__FUNCTION__, y, h); |
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y = MIN(y, s->height); |
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h = s->height - y; |
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} |
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line = h; |
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bypl = s->bypp * s->width; |
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width = s->bypp * w; |
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start = s->bypp * x + bypl * y; |
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src = s->vga.vram_ptr + start; |
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dst = ds_get_data(s->vga.ds) + start; |
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for (; line > 0; line --, src += bypl, dst += bypl) |
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memcpy(dst, src, width); |
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#endif
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dpy_update(s->vga.ds, x, y, w, h); |
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} |
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static inline void vmsvga_update_screen(struct vmsvga_state_s *s) |
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{ |
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#ifndef DIRECT_VRAM
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memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height); |
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#endif
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dpy_update(s->vga.ds, 0, 0, s->width, s->height); |
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} |
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#ifdef DIRECT_VRAM
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# define vmsvga_update_rect_delayed vmsvga_update_rect
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#else
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static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
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s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
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rect->x = x; |
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rect->y = y; |
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rect->w = w; |
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rect->h = h; |
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} |
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#endif
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static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
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{ |
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struct vmsvga_rect_s *rect;
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if (s->invalidated) {
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s->redraw_fifo_first = s->redraw_fifo_last; |
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return;
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} |
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/* Overlapping region updates can be optimised out here - if someone
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* knows a smart algorithm to do that, please share. */
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while (s->redraw_fifo_first != s->redraw_fifo_last) {
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rect = &s->redraw_fifo[s->redraw_fifo_first ++]; |
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s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
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vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
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} |
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} |
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#ifdef HW_RECT_ACCEL
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static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
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int x0, int y0, int x1, int y1, int w, int h) |
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{ |
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# ifdef DIRECT_VRAM
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uint8_t *vram = ds_get_data(s->ds); |
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# else
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uint8_t *vram = s->vga.vram_ptr; |
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# endif
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int bypl = s->bypp * s->width;
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int width = s->bypp * w;
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int line = h;
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uint8_t *ptr[2];
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# ifdef DIRECT_VRAM
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if (s->ds->dpy_copy)
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qemu_console_copy(s->ds, x0, y0, x1, y1, w, h); |
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else
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# endif
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{ |
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if (y1 > y0) {
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ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); |
397 |
ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); |
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for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) |
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memmove(ptr[1], ptr[0], width); |
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} else {
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ptr[0] = vram + s->bypp * x0 + bypl * y0;
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ptr[1] = vram + s->bypp * x1 + bypl * y1;
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for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) |
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memmove(ptr[1], ptr[0], width); |
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} |
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} |
407 |
|
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vmsvga_update_rect_delayed(s, x1, y1, w, h); |
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} |
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#endif
|
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|
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#ifdef HW_FILL_ACCEL
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static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
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uint32_t c, int x, int y, int w, int h) |
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{ |
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# ifdef DIRECT_VRAM
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uint8_t *vram = ds_get_data(s->ds); |
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# else
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uint8_t *vram = s->vga.vram_ptr; |
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# endif
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int bypp = s->bypp;
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int bypl = bypp * s->width;
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int width = bypp * w;
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int line = h;
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int column;
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uint8_t *fst = vram + bypp * x + bypl * y; |
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uint8_t *dst; |
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uint8_t *src; |
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uint8_t col[4];
|
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|
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# ifdef DIRECT_VRAM
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if (s->ds->dpy_fill)
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s->ds->dpy_fill(s->ds, x, y, w, h, c); |
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else
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# endif
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{ |
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col[0] = c;
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col[1] = c >> 8; |
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col[2] = c >> 16; |
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col[3] = c >> 24; |
441 |
|
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if (line --) {
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dst = fst; |
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src = col; |
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for (column = width; column > 0; column --) { |
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*(dst ++) = *(src ++); |
447 |
if (src - col == bypp)
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src = col; |
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} |
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dst = fst; |
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for (; line > 0; line --) { |
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dst += bypl; |
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memcpy(dst, fst, width); |
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} |
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} |
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} |
457 |
|
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vmsvga_update_rect_delayed(s, x, y, w, h); |
459 |
} |
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#endif
|
461 |
|
462 |
struct vmsvga_cursor_definition_s {
|
463 |
int width;
|
464 |
int height;
|
465 |
int id;
|
466 |
int bpp;
|
467 |
int hot_x;
|
468 |
int hot_y;
|
469 |
uint32_t mask[1024];
|
470 |
uint32_t image[4096];
|
471 |
}; |
472 |
|
473 |
#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
474 |
#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
475 |
|
476 |
#ifdef HW_MOUSE_ACCEL
|
477 |
static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
478 |
struct vmsvga_cursor_definition_s *c)
|
479 |
{ |
480 |
QEMUCursor *qc; |
481 |
int i, pixels;
|
482 |
|
483 |
qc = cursor_alloc(c->width, c->height); |
484 |
qc->hot_x = c->hot_x; |
485 |
qc->hot_y = c->hot_y; |
486 |
switch (c->bpp) {
|
487 |
case 1: |
488 |
cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image, |
489 |
1, (void*)c->mask); |
490 |
#ifdef DEBUG
|
491 |
cursor_print_ascii_art(qc, "vmware/mono");
|
492 |
#endif
|
493 |
break;
|
494 |
case 32: |
495 |
/* fill alpha channel from mask, set color to zero */
|
496 |
cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask, |
497 |
1, (void*)c->mask); |
498 |
/* add in rgb values */
|
499 |
pixels = c->width * c->height; |
500 |
for (i = 0; i < pixels; i++) { |
501 |
qc->data[i] |= c->image[i] & 0xffffff;
|
502 |
} |
503 |
#ifdef DEBUG
|
504 |
cursor_print_ascii_art(qc, "vmware/32bit");
|
505 |
#endif
|
506 |
break;
|
507 |
default:
|
508 |
fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
|
509 |
__FUNCTION__, c->bpp); |
510 |
cursor_put(qc); |
511 |
qc = cursor_builtin_left_ptr(); |
512 |
} |
513 |
|
514 |
if (s->vga.ds->cursor_define)
|
515 |
s->vga.ds->cursor_define(qc); |
516 |
cursor_put(qc); |
517 |
} |
518 |
#endif
|
519 |
|
520 |
#define CMD(f) le32_to_cpu(s->cmd->f)
|
521 |
|
522 |
static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s) |
523 |
{ |
524 |
if (!s->config || !s->enable)
|
525 |
return 1; |
526 |
return (s->cmd->next_cmd == s->cmd->stop);
|
527 |
} |
528 |
|
529 |
static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
530 |
{ |
531 |
uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
532 |
s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
533 |
if (CMD(stop) >= CMD(max))
|
534 |
s->cmd->stop = s->cmd->min; |
535 |
return cmd;
|
536 |
} |
537 |
|
538 |
static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
539 |
{ |
540 |
return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
541 |
} |
542 |
|
543 |
static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
544 |
{ |
545 |
uint32_t cmd, colour; |
546 |
int args = 0; |
547 |
int x, y, dx, dy, width, height;
|
548 |
struct vmsvga_cursor_definition_s cursor;
|
549 |
while (!vmsvga_fifo_empty(s))
|
550 |
switch (cmd = vmsvga_fifo_read(s)) {
|
551 |
case SVGA_CMD_UPDATE:
|
552 |
case SVGA_CMD_UPDATE_VERBOSE:
|
553 |
x = vmsvga_fifo_read(s); |
554 |
y = vmsvga_fifo_read(s); |
555 |
width = vmsvga_fifo_read(s); |
556 |
height = vmsvga_fifo_read(s); |
557 |
vmsvga_update_rect_delayed(s, x, y, width, height); |
558 |
break;
|
559 |
|
560 |
case SVGA_CMD_RECT_FILL:
|
561 |
colour = vmsvga_fifo_read(s); |
562 |
x = vmsvga_fifo_read(s); |
563 |
y = vmsvga_fifo_read(s); |
564 |
width = vmsvga_fifo_read(s); |
565 |
height = vmsvga_fifo_read(s); |
566 |
#ifdef HW_FILL_ACCEL
|
567 |
vmsvga_fill_rect(s, colour, x, y, width, height); |
568 |
break;
|
569 |
#else
|
570 |
goto badcmd;
|
571 |
#endif
|
572 |
|
573 |
case SVGA_CMD_RECT_COPY:
|
574 |
x = vmsvga_fifo_read(s); |
575 |
y = vmsvga_fifo_read(s); |
576 |
dx = vmsvga_fifo_read(s); |
577 |
dy = vmsvga_fifo_read(s); |
578 |
width = vmsvga_fifo_read(s); |
579 |
height = vmsvga_fifo_read(s); |
580 |
#ifdef HW_RECT_ACCEL
|
581 |
vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
582 |
break;
|
583 |
#else
|
584 |
goto badcmd;
|
585 |
#endif
|
586 |
|
587 |
case SVGA_CMD_DEFINE_CURSOR:
|
588 |
cursor.id = vmsvga_fifo_read(s); |
589 |
cursor.hot_x = vmsvga_fifo_read(s); |
590 |
cursor.hot_y = vmsvga_fifo_read(s); |
591 |
cursor.width = x = vmsvga_fifo_read(s); |
592 |
cursor.height = y = vmsvga_fifo_read(s); |
593 |
vmsvga_fifo_read(s); |
594 |
cursor.bpp = vmsvga_fifo_read(s); |
595 |
|
596 |
if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || |
597 |
SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
|
598 |
args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
599 |
goto badcmd;
|
600 |
} |
601 |
|
602 |
for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) |
603 |
cursor.mask[args] = vmsvga_fifo_read_raw(s); |
604 |
for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) |
605 |
cursor.image[args] = vmsvga_fifo_read_raw(s); |
606 |
#ifdef HW_MOUSE_ACCEL
|
607 |
vmsvga_cursor_define(s, &cursor); |
608 |
break;
|
609 |
#else
|
610 |
args = 0;
|
611 |
goto badcmd;
|
612 |
#endif
|
613 |
|
614 |
/*
|
615 |
* Other commands that we at least know the number of arguments
|
616 |
* for so we can avoid FIFO desync if driver uses them illegally.
|
617 |
*/
|
618 |
case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
619 |
vmsvga_fifo_read(s); |
620 |
vmsvga_fifo_read(s); |
621 |
vmsvga_fifo_read(s); |
622 |
x = vmsvga_fifo_read(s); |
623 |
y = vmsvga_fifo_read(s); |
624 |
args = x * y; |
625 |
goto badcmd;
|
626 |
case SVGA_CMD_RECT_ROP_FILL:
|
627 |
args = 6;
|
628 |
goto badcmd;
|
629 |
case SVGA_CMD_RECT_ROP_COPY:
|
630 |
args = 7;
|
631 |
goto badcmd;
|
632 |
case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
633 |
vmsvga_fifo_read(s); |
634 |
vmsvga_fifo_read(s); |
635 |
args = 7 + (vmsvga_fifo_read(s) >> 2); |
636 |
goto badcmd;
|
637 |
case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
638 |
args = 12;
|
639 |
goto badcmd;
|
640 |
|
641 |
/*
|
642 |
* Other commands that are not listed as depending on any
|
643 |
* CAPABILITIES bits, but are not described in the README either.
|
644 |
*/
|
645 |
case SVGA_CMD_SURFACE_FILL:
|
646 |
case SVGA_CMD_SURFACE_COPY:
|
647 |
case SVGA_CMD_FRONT_ROP_FILL:
|
648 |
case SVGA_CMD_FENCE:
|
649 |
case SVGA_CMD_INVALID_CMD:
|
650 |
break; /* Nop */ |
651 |
|
652 |
default:
|
653 |
badcmd:
|
654 |
while (args --)
|
655 |
vmsvga_fifo_read(s); |
656 |
printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
657 |
__FUNCTION__, cmd); |
658 |
break;
|
659 |
} |
660 |
|
661 |
s->syncing = 0;
|
662 |
} |
663 |
|
664 |
static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
665 |
{ |
666 |
struct vmsvga_state_s *s = opaque;
|
667 |
return s->index;
|
668 |
} |
669 |
|
670 |
static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
671 |
{ |
672 |
struct vmsvga_state_s *s = opaque;
|
673 |
s->index = index; |
674 |
} |
675 |
|
676 |
static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
677 |
{ |
678 |
uint32_t caps; |
679 |
struct vmsvga_state_s *s = opaque;
|
680 |
switch (s->index) {
|
681 |
case SVGA_REG_ID:
|
682 |
return s->svgaid;
|
683 |
|
684 |
case SVGA_REG_ENABLE:
|
685 |
return s->enable;
|
686 |
|
687 |
case SVGA_REG_WIDTH:
|
688 |
return s->width;
|
689 |
|
690 |
case SVGA_REG_HEIGHT:
|
691 |
return s->height;
|
692 |
|
693 |
case SVGA_REG_MAX_WIDTH:
|
694 |
return SVGA_MAX_WIDTH;
|
695 |
|
696 |
case SVGA_REG_MAX_HEIGHT:
|
697 |
return SVGA_MAX_HEIGHT;
|
698 |
|
699 |
case SVGA_REG_DEPTH:
|
700 |
return s->depth;
|
701 |
|
702 |
case SVGA_REG_BITS_PER_PIXEL:
|
703 |
return (s->depth + 7) & ~7; |
704 |
|
705 |
case SVGA_REG_PSEUDOCOLOR:
|
706 |
return 0x0; |
707 |
|
708 |
case SVGA_REG_RED_MASK:
|
709 |
return s->wred;
|
710 |
case SVGA_REG_GREEN_MASK:
|
711 |
return s->wgreen;
|
712 |
case SVGA_REG_BLUE_MASK:
|
713 |
return s->wblue;
|
714 |
|
715 |
case SVGA_REG_BYTES_PER_LINE:
|
716 |
return ((s->depth + 7) >> 3) * s->new_width; |
717 |
|
718 |
case SVGA_REG_FB_START:
|
719 |
return s->vram_base;
|
720 |
|
721 |
case SVGA_REG_FB_OFFSET:
|
722 |
return 0x0; |
723 |
|
724 |
case SVGA_REG_VRAM_SIZE:
|
725 |
return s->vga.vram_size;
|
726 |
|
727 |
case SVGA_REG_FB_SIZE:
|
728 |
return s->fb_size;
|
729 |
|
730 |
case SVGA_REG_CAPABILITIES:
|
731 |
caps = SVGA_CAP_NONE; |
732 |
#ifdef HW_RECT_ACCEL
|
733 |
caps |= SVGA_CAP_RECT_COPY; |
734 |
#endif
|
735 |
#ifdef HW_FILL_ACCEL
|
736 |
caps |= SVGA_CAP_RECT_FILL; |
737 |
#endif
|
738 |
#ifdef HW_MOUSE_ACCEL
|
739 |
if (s->vga.ds->mouse_set)
|
740 |
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
741 |
SVGA_CAP_CURSOR_BYPASS; |
742 |
#endif
|
743 |
return caps;
|
744 |
|
745 |
case SVGA_REG_MEM_START:
|
746 |
return s->fifo_base;
|
747 |
|
748 |
case SVGA_REG_MEM_SIZE:
|
749 |
return s->fifo_size;
|
750 |
|
751 |
case SVGA_REG_CONFIG_DONE:
|
752 |
return s->config;
|
753 |
|
754 |
case SVGA_REG_SYNC:
|
755 |
case SVGA_REG_BUSY:
|
756 |
return s->syncing;
|
757 |
|
758 |
case SVGA_REG_GUEST_ID:
|
759 |
return s->guest;
|
760 |
|
761 |
case SVGA_REG_CURSOR_ID:
|
762 |
return s->cursor.id;
|
763 |
|
764 |
case SVGA_REG_CURSOR_X:
|
765 |
return s->cursor.x;
|
766 |
|
767 |
case SVGA_REG_CURSOR_Y:
|
768 |
return s->cursor.x;
|
769 |
|
770 |
case SVGA_REG_CURSOR_ON:
|
771 |
return s->cursor.on;
|
772 |
|
773 |
case SVGA_REG_HOST_BITS_PER_PIXEL:
|
774 |
return (s->depth + 7) & ~7; |
775 |
|
776 |
case SVGA_REG_SCRATCH_SIZE:
|
777 |
return s->scratch_size;
|
778 |
|
779 |
case SVGA_REG_MEM_REGS:
|
780 |
case SVGA_REG_NUM_DISPLAYS:
|
781 |
case SVGA_REG_PITCHLOCK:
|
782 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
783 |
return 0; |
784 |
|
785 |
default:
|
786 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
787 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) |
788 |
return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
789 |
printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
790 |
} |
791 |
|
792 |
return 0; |
793 |
} |
794 |
|
795 |
static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
796 |
{ |
797 |
struct vmsvga_state_s *s = opaque;
|
798 |
switch (s->index) {
|
799 |
case SVGA_REG_ID:
|
800 |
if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
|
801 |
s->svgaid = value; |
802 |
break;
|
803 |
|
804 |
case SVGA_REG_ENABLE:
|
805 |
s->enable = value; |
806 |
s->config &= !!value; |
807 |
s->width = -1;
|
808 |
s->height = -1;
|
809 |
s->invalidated = 1;
|
810 |
s->vga.invalidate(&s->vga); |
811 |
if (s->enable) {
|
812 |
s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; |
813 |
vga_dirty_log_stop(&s->vga); |
814 |
} else {
|
815 |
vga_dirty_log_start(&s->vga); |
816 |
} |
817 |
break;
|
818 |
|
819 |
case SVGA_REG_WIDTH:
|
820 |
s->new_width = value; |
821 |
s->invalidated = 1;
|
822 |
break;
|
823 |
|
824 |
case SVGA_REG_HEIGHT:
|
825 |
s->new_height = value; |
826 |
s->invalidated = 1;
|
827 |
break;
|
828 |
|
829 |
case SVGA_REG_DEPTH:
|
830 |
case SVGA_REG_BITS_PER_PIXEL:
|
831 |
if (value != s->depth) {
|
832 |
printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
|
833 |
s->config = 0;
|
834 |
} |
835 |
break;
|
836 |
|
837 |
case SVGA_REG_CONFIG_DONE:
|
838 |
if (value) {
|
839 |
s->fifo = (uint32_t *) s->fifo_ptr; |
840 |
/* Check range and alignment. */
|
841 |
if ((CMD(min) | CMD(max) |
|
842 |
CMD(next_cmd) | CMD(stop)) & 3)
|
843 |
break;
|
844 |
if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
|
845 |
break;
|
846 |
if (CMD(max) > SVGA_FIFO_SIZE)
|
847 |
break;
|
848 |
if (CMD(max) < CMD(min) + 10 * 1024) |
849 |
break;
|
850 |
} |
851 |
s->config = !!value; |
852 |
break;
|
853 |
|
854 |
case SVGA_REG_SYNC:
|
855 |
s->syncing = 1;
|
856 |
vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
857 |
break;
|
858 |
|
859 |
case SVGA_REG_GUEST_ID:
|
860 |
s->guest = value; |
861 |
#ifdef VERBOSE
|
862 |
if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
863 |
ARRAY_SIZE(vmsvga_guest_id)) |
864 |
printf("%s: guest runs %s.\n", __FUNCTION__,
|
865 |
vmsvga_guest_id[value - GUEST_OS_BASE]); |
866 |
#endif
|
867 |
break;
|
868 |
|
869 |
case SVGA_REG_CURSOR_ID:
|
870 |
s->cursor.id = value; |
871 |
break;
|
872 |
|
873 |
case SVGA_REG_CURSOR_X:
|
874 |
s->cursor.x = value; |
875 |
break;
|
876 |
|
877 |
case SVGA_REG_CURSOR_Y:
|
878 |
s->cursor.y = value; |
879 |
break;
|
880 |
|
881 |
case SVGA_REG_CURSOR_ON:
|
882 |
s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
883 |
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
884 |
#ifdef HW_MOUSE_ACCEL
|
885 |
if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
|
886 |
s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); |
887 |
#endif
|
888 |
break;
|
889 |
|
890 |
case SVGA_REG_MEM_REGS:
|
891 |
case SVGA_REG_NUM_DISPLAYS:
|
892 |
case SVGA_REG_PITCHLOCK:
|
893 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
894 |
break;
|
895 |
|
896 |
default:
|
897 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
898 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
899 |
s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
900 |
break;
|
901 |
} |
902 |
printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
903 |
} |
904 |
} |
905 |
|
906 |
static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
907 |
{ |
908 |
printf("%s: what are we supposed to return?\n", __FUNCTION__);
|
909 |
return 0xcafe; |
910 |
} |
911 |
|
912 |
static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
913 |
{ |
914 |
printf("%s: what are we supposed to do with (%08x)?\n",
|
915 |
__FUNCTION__, data); |
916 |
} |
917 |
|
918 |
static inline void vmsvga_size(struct vmsvga_state_s *s) |
919 |
{ |
920 |
if (s->new_width != s->width || s->new_height != s->height) {
|
921 |
s->width = s->new_width; |
922 |
s->height = s->new_height; |
923 |
qemu_console_resize(s->vga.ds, s->width, s->height); |
924 |
s->invalidated = 1;
|
925 |
} |
926 |
} |
927 |
|
928 |
static void vmsvga_update_display(void *opaque) |
929 |
{ |
930 |
struct vmsvga_state_s *s = opaque;
|
931 |
if (!s->enable) {
|
932 |
s->vga.update(&s->vga); |
933 |
return;
|
934 |
} |
935 |
|
936 |
vmsvga_size(s); |
937 |
|
938 |
vmsvga_fifo_run(s); |
939 |
vmsvga_update_rect_flush(s); |
940 |
|
941 |
/*
|
942 |
* Is it more efficient to look at vram VGA-dirty bits or wait
|
943 |
* for the driver to issue SVGA_CMD_UPDATE?
|
944 |
*/
|
945 |
if (s->invalidated) {
|
946 |
s->invalidated = 0;
|
947 |
vmsvga_update_screen(s); |
948 |
} |
949 |
} |
950 |
|
951 |
static void vmsvga_reset(struct vmsvga_state_s *s) |
952 |
{ |
953 |
s->index = 0;
|
954 |
s->enable = 0;
|
955 |
s->config = 0;
|
956 |
s->width = -1;
|
957 |
s->height = -1;
|
958 |
s->svgaid = SVGA_ID; |
959 |
s->depth = ds_get_bits_per_pixel(s->vga.ds); |
960 |
s->bypp = ds_get_bytes_per_pixel(s->vga.ds); |
961 |
s->cursor.on = 0;
|
962 |
s->redraw_fifo_first = 0;
|
963 |
s->redraw_fifo_last = 0;
|
964 |
switch (s->depth) {
|
965 |
case 8: |
966 |
s->wred = 0x00000007;
|
967 |
s->wgreen = 0x00000038;
|
968 |
s->wblue = 0x000000c0;
|
969 |
break;
|
970 |
case 15: |
971 |
s->wred = 0x0000001f;
|
972 |
s->wgreen = 0x000003e0;
|
973 |
s->wblue = 0x00007c00;
|
974 |
break;
|
975 |
case 16: |
976 |
s->wred = 0x0000001f;
|
977 |
s->wgreen = 0x000007e0;
|
978 |
s->wblue = 0x0000f800;
|
979 |
break;
|
980 |
case 24: |
981 |
s->wred = 0x00ff0000;
|
982 |
s->wgreen = 0x0000ff00;
|
983 |
s->wblue = 0x000000ff;
|
984 |
break;
|
985 |
case 32: |
986 |
s->wred = 0x00ff0000;
|
987 |
s->wgreen = 0x0000ff00;
|
988 |
s->wblue = 0x000000ff;
|
989 |
break;
|
990 |
} |
991 |
s->syncing = 0;
|
992 |
|
993 |
vga_dirty_log_start(&s->vga); |
994 |
} |
995 |
|
996 |
static void vmsvga_invalidate_display(void *opaque) |
997 |
{ |
998 |
struct vmsvga_state_s *s = opaque;
|
999 |
if (!s->enable) {
|
1000 |
s->vga.invalidate(&s->vga); |
1001 |
return;
|
1002 |
} |
1003 |
|
1004 |
s->invalidated = 1;
|
1005 |
} |
1006 |
|
1007 |
/* save the vga display in a PPM image even if no display is
|
1008 |
available */
|
1009 |
static void vmsvga_screen_dump(void *opaque, const char *filename) |
1010 |
{ |
1011 |
struct vmsvga_state_s *s = opaque;
|
1012 |
if (!s->enable) {
|
1013 |
s->vga.screen_dump(&s->vga, filename); |
1014 |
return;
|
1015 |
} |
1016 |
|
1017 |
if (s->depth == 32) { |
1018 |
DisplaySurface *ds = qemu_create_displaysurface_from(s->width, |
1019 |
s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
|
1020 |
ppm_save(filename, ds); |
1021 |
qemu_free(ds); |
1022 |
} |
1023 |
} |
1024 |
|
1025 |
static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
1026 |
{ |
1027 |
struct vmsvga_state_s *s = opaque;
|
1028 |
|
1029 |
if (s->vga.text_update)
|
1030 |
s->vga.text_update(&s->vga, chardata); |
1031 |
} |
1032 |
|
1033 |
#ifdef DIRECT_VRAM
|
1034 |
static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) |
1035 |
{ |
1036 |
struct vmsvga_state_s *s = opaque;
|
1037 |
if (addr < s->fb_size)
|
1038 |
return *(uint8_t *) (ds_get_data(s->ds) + addr);
|
1039 |
else
|
1040 |
return *(uint8_t *) (s->vram_ptr + addr);
|
1041 |
} |
1042 |
|
1043 |
static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) |
1044 |
{ |
1045 |
struct vmsvga_state_s *s = opaque;
|
1046 |
if (addr < s->fb_size)
|
1047 |
return *(uint16_t *) (ds_get_data(s->ds) + addr);
|
1048 |
else
|
1049 |
return *(uint16_t *) (s->vram_ptr + addr);
|
1050 |
} |
1051 |
|
1052 |
static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) |
1053 |
{ |
1054 |
struct vmsvga_state_s *s = opaque;
|
1055 |
if (addr < s->fb_size)
|
1056 |
return *(uint32_t *) (ds_get_data(s->ds) + addr);
|
1057 |
else
|
1058 |
return *(uint32_t *) (s->vram_ptr + addr);
|
1059 |
} |
1060 |
|
1061 |
static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, |
1062 |
uint32_t value) |
1063 |
{ |
1064 |
struct vmsvga_state_s *s = opaque;
|
1065 |
if (addr < s->fb_size)
|
1066 |
*(uint8_t *) (ds_get_data(s->ds) + addr) = value; |
1067 |
else
|
1068 |
*(uint8_t *) (s->vram_ptr + addr) = value; |
1069 |
} |
1070 |
|
1071 |
static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, |
1072 |
uint32_t value) |
1073 |
{ |
1074 |
struct vmsvga_state_s *s = opaque;
|
1075 |
if (addr < s->fb_size)
|
1076 |
*(uint16_t *) (ds_get_data(s->ds) + addr) = value; |
1077 |
else
|
1078 |
*(uint16_t *) (s->vram_ptr + addr) = value; |
1079 |
} |
1080 |
|
1081 |
static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, |
1082 |
uint32_t value) |
1083 |
{ |
1084 |
struct vmsvga_state_s *s = opaque;
|
1085 |
if (addr < s->fb_size)
|
1086 |
*(uint32_t *) (ds_get_data(s->ds) + addr) = value; |
1087 |
else
|
1088 |
*(uint32_t *) (s->vram_ptr + addr) = value; |
1089 |
} |
1090 |
|
1091 |
static CPUReadMemoryFunc * const vmsvga_vram_read[] = { |
1092 |
vmsvga_vram_readb, |
1093 |
vmsvga_vram_readw, |
1094 |
vmsvga_vram_readl, |
1095 |
}; |
1096 |
|
1097 |
static CPUWriteMemoryFunc * const vmsvga_vram_write[] = { |
1098 |
vmsvga_vram_writeb, |
1099 |
vmsvga_vram_writew, |
1100 |
vmsvga_vram_writel, |
1101 |
}; |
1102 |
#endif
|
1103 |
|
1104 |
static int vmsvga_post_load(void *opaque, int version_id) |
1105 |
{ |
1106 |
struct vmsvga_state_s *s = opaque;
|
1107 |
|
1108 |
s->invalidated = 1;
|
1109 |
if (s->config)
|
1110 |
s->fifo = (uint32_t *) s->fifo_ptr; |
1111 |
|
1112 |
return 0; |
1113 |
} |
1114 |
|
1115 |
static const VMStateDescription vmstate_vmware_vga_internal = { |
1116 |
.name = "vmware_vga_internal",
|
1117 |
.version_id = 0,
|
1118 |
.minimum_version_id = 0,
|
1119 |
.minimum_version_id_old = 0,
|
1120 |
.post_load = vmsvga_post_load, |
1121 |
.fields = (VMStateField []) { |
1122 |
VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
|
1123 |
VMSTATE_INT32(enable, struct vmsvga_state_s),
|
1124 |
VMSTATE_INT32(config, struct vmsvga_state_s),
|
1125 |
VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
|
1126 |
VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
|
1127 |
VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
|
1128 |
VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
|
1129 |
VMSTATE_INT32(index, struct vmsvga_state_s),
|
1130 |
VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
|
1131 |
scratch_size, 0, vmstate_info_uint32, uint32_t),
|
1132 |
VMSTATE_INT32(new_width, struct vmsvga_state_s),
|
1133 |
VMSTATE_INT32(new_height, struct vmsvga_state_s),
|
1134 |
VMSTATE_UINT32(guest, struct vmsvga_state_s),
|
1135 |
VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
|
1136 |
VMSTATE_INT32(syncing, struct vmsvga_state_s),
|
1137 |
VMSTATE_INT32(fb_size, struct vmsvga_state_s),
|
1138 |
VMSTATE_END_OF_LIST() |
1139 |
} |
1140 |
}; |
1141 |
|
1142 |
static const VMStateDescription vmstate_vmware_vga = { |
1143 |
.name = "vmware_vga",
|
1144 |
.version_id = 0,
|
1145 |
.minimum_version_id = 0,
|
1146 |
.minimum_version_id_old = 0,
|
1147 |
.fields = (VMStateField []) { |
1148 |
VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
|
1149 |
VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1150 |
vmstate_vmware_vga_internal, struct vmsvga_state_s),
|
1151 |
VMSTATE_END_OF_LIST() |
1152 |
} |
1153 |
}; |
1154 |
|
1155 |
static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size) |
1156 |
{ |
1157 |
s->scratch_size = SVGA_SCRATCH_SIZE; |
1158 |
s->scratch = qemu_malloc(s->scratch_size * 4);
|
1159 |
|
1160 |
s->vga.ds = graphic_console_init(vmsvga_update_display, |
1161 |
vmsvga_invalidate_display, |
1162 |
vmsvga_screen_dump, |
1163 |
vmsvga_text_update, s); |
1164 |
|
1165 |
|
1166 |
s->fifo_size = SVGA_FIFO_SIZE; |
1167 |
s->fifo_offset = qemu_ram_alloc(NULL, "vmsvga.fifo", s->fifo_size); |
1168 |
s->fifo_ptr = qemu_get_ram_ptr(s->fifo_offset); |
1169 |
|
1170 |
vga_common_init(&s->vga, vga_ram_size); |
1171 |
vga_init(&s->vga); |
1172 |
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); |
1173 |
|
1174 |
vga_init_vbe(&s->vga); |
1175 |
|
1176 |
rom_add_vga(VGABIOS_FILENAME); |
1177 |
|
1178 |
vmsvga_reset(s); |
1179 |
} |
1180 |
|
1181 |
static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num, |
1182 |
pcibus_t addr, pcibus_t size, int type)
|
1183 |
{ |
1184 |
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1185 |
struct vmsvga_state_s *s = &d->chip;
|
1186 |
|
1187 |
register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1188 |
1, 4, vmsvga_index_read, s); |
1189 |
register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1190 |
1, 4, vmsvga_index_write, s); |
1191 |
register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1192 |
1, 4, vmsvga_value_read, s); |
1193 |
register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1194 |
1, 4, vmsvga_value_write, s); |
1195 |
register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1196 |
1, 4, vmsvga_bios_read, s); |
1197 |
register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1198 |
1, 4, vmsvga_bios_write, s); |
1199 |
} |
1200 |
|
1201 |
static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, |
1202 |
pcibus_t addr, pcibus_t size, int type)
|
1203 |
{ |
1204 |
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1205 |
struct vmsvga_state_s *s = &d->chip;
|
1206 |
ram_addr_t iomemtype; |
1207 |
|
1208 |
s->vram_base = addr; |
1209 |
#ifdef DIRECT_VRAM
|
1210 |
iomemtype = cpu_register_io_memory(vmsvga_vram_read, |
1211 |
vmsvga_vram_write, s); |
1212 |
#else
|
1213 |
iomemtype = s->vga.vram_offset | IO_MEM_RAM; |
1214 |
#endif
|
1215 |
cpu_register_physical_memory(s->vram_base, s->vga.vram_size, |
1216 |
iomemtype); |
1217 |
|
1218 |
s->vga.map_addr = addr; |
1219 |
s->vga.map_end = addr + s->vga.vram_size; |
1220 |
vga_dirty_log_restart(&s->vga); |
1221 |
} |
1222 |
|
1223 |
static void pci_vmsvga_map_fifo(PCIDevice *pci_dev, int region_num, |
1224 |
pcibus_t addr, pcibus_t size, int type)
|
1225 |
{ |
1226 |
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1227 |
struct vmsvga_state_s *s = &d->chip;
|
1228 |
ram_addr_t iomemtype; |
1229 |
|
1230 |
s->fifo_base = addr; |
1231 |
iomemtype = s->fifo_offset | IO_MEM_RAM; |
1232 |
cpu_register_physical_memory(s->fifo_base, s->fifo_size, |
1233 |
iomemtype); |
1234 |
} |
1235 |
|
1236 |
static int pci_vmsvga_initfn(PCIDevice *dev) |
1237 |
{ |
1238 |
struct pci_vmsvga_state_s *s =
|
1239 |
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
|
1240 |
|
1241 |
pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE); |
1242 |
pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID); |
1243 |
s->card.config[PCI_COMMAND] = PCI_COMMAND_IO | |
1244 |
PCI_COMMAND_MEMORY | |
1245 |
PCI_COMMAND_MASTER; /* I/O + Memory */
|
1246 |
pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA); |
1247 |
s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ |
1248 |
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ |
1249 |
s->card.config[PCI_SUBSYSTEM_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
|
1250 |
s->card.config[PCI_SUBSYSTEM_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8; |
1251 |
s->card.config[PCI_SUBSYSTEM_ID] = SVGA_PCI_DEVICE_ID & 0xff;
|
1252 |
s->card.config[PCI_SUBSYSTEM_ID + 1] = SVGA_PCI_DEVICE_ID >> 8; |
1253 |
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ |
1254 |
|
1255 |
pci_register_bar(&s->card, 0, 0x10, |
1256 |
PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport); |
1257 |
pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
|
1258 |
PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem); |
1259 |
|
1260 |
pci_register_bar(&s->card, 2, SVGA_FIFO_SIZE,
|
1261 |
PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_fifo); |
1262 |
|
1263 |
vmsvga_init(&s->chip, VGA_RAM_SIZE); |
1264 |
|
1265 |
return 0; |
1266 |
} |
1267 |
|
1268 |
void pci_vmsvga_init(PCIBus *bus)
|
1269 |
{ |
1270 |
pci_create_simple(bus, -1, "vmware-svga"); |
1271 |
} |
1272 |
|
1273 |
static PCIDeviceInfo vmsvga_info = {
|
1274 |
.qdev.name = "vmware-svga",
|
1275 |
.qdev.size = sizeof(struct pci_vmsvga_state_s), |
1276 |
.qdev.vmsd = &vmstate_vmware_vga, |
1277 |
.init = pci_vmsvga_initfn, |
1278 |
}; |
1279 |
|
1280 |
static void vmsvga_register(void) |
1281 |
{ |
1282 |
pci_qdev_register(&vmsvga_info); |
1283 |
} |
1284 |
device_init(vmsvga_register); |