Revision b8b6a50b target-i386/op.c
| b/target-i386/op.c | ||
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| 276 | 276 |
#ifdef TARGET_X86_64 |
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void OPPROTO op_mulq_EAX_T0(void) |
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{
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helper_mulq_EAX_T0(); |
|
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helper_mulq_EAX_T0(T0);
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} |
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void OPPROTO op_imulq_EAX_T0(void) |
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{
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helper_imulq_EAX_T0(); |
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helper_imulq_EAX_T0(T0);
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} |
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void OPPROTO op_imulq_T0_T1(void) |
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{
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helper_imulq_T0_T1();
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T0 = helper_imulq_T0_T1(T0, T1);
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} |
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#endif |
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|
| ... | ... | |
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void OPPROTO op_cmpxchg8b(void) |
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{
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helper_cmpxchg8b(); |
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helper_cmpxchg8b(A0);
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} |
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/* multiple size ops */ |
| ... | ... | |
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/* segment handling */ |
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/* never use it with R_CS */ |
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void OPPROTO op_movl_seg_T0(void) |
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{
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helper_load_seg(PARAM1, T0); |
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} |
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/* faster VM86 version */ |
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void OPPROTO op_movl_seg_T0_vm(void) |
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{
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| ... | ... | |
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void OPPROTO op_lsl(void) |
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{
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helper_lsl(T0); |
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uint32_t val; |
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val = helper_lsl(T0); |
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if (CC_SRC & CC_Z) |
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T1 = val; |
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FORCE_RET(); |
|
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} |
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void OPPROTO op_lar(void) |
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{
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helper_lar(T0); |
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uint32_t val; |
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val = helper_lar(T0); |
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if (CC_SRC & CC_Z) |
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T1 = val; |
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FORCE_RET(); |
|
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} |
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|
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void OPPROTO op_verr(void) |
| ... | ... | |
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CC_SRC = (eflags & ~CC_Z) | T1; |
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} |
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/* T0: segment, T1:eip */ |
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void OPPROTO op_ljmp_protected_T0_T1(void) |
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{
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helper_ljmp_protected_T0_T1(PARAM1); |
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} |
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void OPPROTO op_lcall_real_T0_T1(void) |
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{
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helper_lcall_real_T0_T1(PARAM1, PARAM2); |
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} |
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void OPPROTO op_lcall_protected_T0_T1(void) |
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{
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helper_lcall_protected_T0_T1(PARAM1, PARAM2); |
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} |
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void OPPROTO op_iret_real(void) |
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{
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helper_iret_real(PARAM1); |
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} |
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void OPPROTO op_iret_protected(void) |
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{
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helper_iret_protected(PARAM1, PARAM2); |
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} |
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void OPPROTO op_lret_protected(void) |
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{
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helper_lret_protected(PARAM1, PARAM2); |
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} |
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/* CR registers access. */ |
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void OPPROTO op_movl_crN_T0(void) |
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{
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helper_movl_crN_T0(PARAM1); |
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} |
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/* These pseudo-opcodes check for SVM intercepts. */ |
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void OPPROTO op_svm_check_intercept(void) |
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{
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A0 = PARAM1 & PARAM2; |
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svm_check_intercept(PARAMQ1); |
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} |
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void OPPROTO op_svm_check_intercept_param(void) |
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{
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A0 = PARAM1 & PARAM2; |
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svm_check_intercept_param(PARAMQ1, T1); |
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} |
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void OPPROTO op_svm_vmexit(void) |
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{
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A0 = PARAM1 & PARAM2; |
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vmexit(PARAMQ1, T1); |
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} |
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void OPPROTO op_geneflags(void) |
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{
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CC_SRC = cc_table[CC_OP].compute_all(); |
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} |
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/* This pseudo-opcode checks for IO intercepts. */ |
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#if !defined(CONFIG_USER_ONLY) |
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void OPPROTO op_svm_check_intercept_io(void) |
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{
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A0 = PARAM1 & PARAM2; |
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/* PARAMQ1 = TYPE (0 = OUT, 1 = IN; 4 = STRING; 8 = REP) |
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T0 = PORT |
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T1 = next eip */ |
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stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), T1); |
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/* ASIZE does not appear on real hw */ |
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svm_check_intercept_param(SVM_EXIT_IOIO, |
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(PARAMQ1 & ~SVM_IOIO_ASIZE_MASK) | |
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((T0 & 0xffff) << 16)); |
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} |
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#endif |
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#if !defined(CONFIG_USER_ONLY) |
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void OPPROTO op_movtl_T0_cr8(void) |
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{
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T0 = cpu_get_apic_tpr(env); |
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} |
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#endif |
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/* DR registers access */ |
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void OPPROTO op_movl_drN_T0(void) |
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{
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helper_movl_drN_T0(PARAM1); |
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} |
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void OPPROTO op_lmsw_T0(void) |
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{
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/* only 4 lower bits of CR0 are modified. PE cannot be set to zero |
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if already set to one. */ |
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T0 = (env->cr[0] & ~0xe) | (T0 & 0xf); |
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helper_movl_crN_T0(0); |
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} |
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|
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void OPPROTO op_movl_T0_env(void) |
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{
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T0 = *(uint32_t *)((char *)env + PARAM1); |
| ... | ... | |
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*(target_ulong *)((char *)env + PARAM1) = T1; |
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} |
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void OPPROTO op_clts(void) |
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{
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env->cr[0] &= ~CR0_TS_MASK; |
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env->hflags &= ~HF_TS_MASK; |
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} |
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/* flags handling */ |
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void OPPROTO op_jmp_label(void) |
| ... | ... | |
| 1028 | 926 |
T0 = 0; |
| 1029 | 927 |
} |
| 1030 | 928 |
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/* threading support */ |
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void OPPROTO op_lock(void) |
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{
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cpu_lock(); |
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} |
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void OPPROTO op_unlock(void) |
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{
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cpu_unlock(); |
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} |
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/* SSE support */ |
| 1043 | 930 |
void OPPROTO op_com_dummy(void) |
| 1044 | 931 |
{
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Also available in: Unified diff