Revision b8cc45d6
| b/target-i386/cpu.h | ||
|---|---|---|
| 734 | 734 |
uint32_t sipi_vector; |
| 735 | 735 |
uint32_t cpuid_kvm_features; |
| 736 | 736 |
uint32_t cpuid_svm_features; |
| 737 |
bool tsc_valid; |
|
| 737 | 738 |
|
| 738 | 739 |
/* in order to simplify APIC support, we leave this pointer to the |
| 739 | 740 |
user */ |
| b/target-i386/kvm.c | ||
|---|---|---|
| 301 | 301 |
#endif |
| 302 | 302 |
} |
| 303 | 303 |
|
| 304 |
static void cpu_update_state(void *opaque, int running, int reason) |
|
| 305 |
{
|
|
| 306 |
CPUState *env = opaque; |
|
| 307 |
|
|
| 308 |
if (running) {
|
|
| 309 |
env->tsc_valid = false; |
|
| 310 |
} |
|
| 311 |
} |
|
| 312 |
|
|
| 304 | 313 |
int kvm_arch_init_vcpu(CPUState *env) |
| 305 | 314 |
{
|
| 306 | 315 |
struct {
|
| ... | ... | |
| 434 | 443 |
} |
| 435 | 444 |
#endif |
| 436 | 445 |
|
| 446 |
qemu_add_vm_change_state_handler(cpu_update_state, env); |
|
| 447 |
|
|
| 437 | 448 |
return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
| 438 | 449 |
} |
| 439 | 450 |
|
| ... | ... | |
| 1061 | 1072 |
if (has_msr_hsave_pa) {
|
| 1062 | 1073 |
msrs[n++].index = MSR_VM_HSAVE_PA; |
| 1063 | 1074 |
} |
| 1064 |
msrs[n++].index = MSR_IA32_TSC; |
|
| 1075 |
|
|
| 1076 |
if (!env->tsc_valid) {
|
|
| 1077 |
msrs[n++].index = MSR_IA32_TSC; |
|
| 1078 |
env->tsc_valid = !vm_running; |
|
| 1079 |
} |
|
| 1080 |
|
|
| 1065 | 1081 |
#ifdef TARGET_X86_64 |
| 1066 | 1082 |
if (lm_capable_kernel) {
|
| 1067 | 1083 |
msrs[n++].index = MSR_CSTAR; |
Also available in: Unified diff