Revision b8e9fc06

b/target-sparc/helper.c
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//#define DEBUG_MMU
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//#define DEBUG_FEATURES
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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    do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_MMU(fmt, ...) do {} while (0)
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#endif
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static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
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/* Sparc MMU emulation */
......
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    for (i = 0; i < 64; i++) {
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        // ctx match, vaddr match, valid?
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        if (ultrasparc_tag_match(&env->dtlb[i],
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                                 address, context, physical)) {
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        if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
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            uint8_t fault_type = 0;
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            // access ok?
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            if (((env->dtlb[i].tte & 0x4) && is_user) ||
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                (!(env->dtlb[i].tte & 0x2) && (rw == 1))) {
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                uint8_t fault_type = 0;
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            if ((env->dtlb[i].tte & 0x4) && is_user) {
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                fault_type |= 1; /* privilege violation */
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                env->exception_index = TT_DFAULT;
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                if ((env->dtlb[i].tte & 0x4) && is_user) {
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                    fault_type |= 1; /* privilege violation */
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                }
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                DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
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                            " mmu_idx=%d tl=%d\n",
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                            address, context, mmu_idx, env->tl);
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            } else if (!(env->dtlb[i].tte & 0x2) && (rw == 1)) {
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                env->exception_index = TT_DPROT;
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                if (env->dmmu.sfsr & 1) /* Fault status register */
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                    env->dmmu.sfsr = 2; /* overflow (not read before
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                DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
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                            " mmu_idx=%d tl=%d\n",
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                            address, context, mmu_idx, env->tl);
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            } else {
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                *prot = PAGE_READ;
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                if (env->dtlb[i].tte & 0x2)
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                    *prot |= PAGE_WRITE;
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                TTE_SET_USED(env->dtlb[i].tte);
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                return 0;
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            }
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            if (env->dmmu.sfsr & 1) /* Fault status register */
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                env->dmmu.sfsr = 2; /* overflow (not read before
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                                             another fault) */
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                env->dmmu.sfsr |= (is_user << 3) | ((rw == 1) << 2) | 1;
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            env->dmmu.sfsr |= (is_user << 3) | ((rw == 1) << 2) | 1;
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                env->dmmu.sfsr |= (fault_type << 7);
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            env->dmmu.sfsr |= (fault_type << 7);
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                env->dmmu.sfar = address; /* Fault address register */
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                env->exception_index = TT_DFAULT;
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#ifdef DEBUG_MMU
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                printf("DFAULT at 0x%" PRIx64 "\n", address);
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#endif
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                return 1;
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            }
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            *prot = PAGE_READ;
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            if (env->dtlb[i].tte & 0x2)
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                *prot |= PAGE_WRITE;
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            TTE_SET_USED(env->dtlb[i].tte);
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            return 0;
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            env->dmmu.sfar = address; /* Fault address register */
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            return 1;
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        }
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    }
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#ifdef DEBUG_MMU
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    printf("DMISS at 0x%" PRIx64 "\n", address);
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#endif
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    DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n",
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                address, context);
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    env->dmmu.tag_access = (address & ~0x1fffULL) | context;
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    env->exception_index = TT_DMISS;
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    return 1;
......
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                                             another fault) */
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                env->immu.sfsr |= (is_user << 3) | 1;
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                env->exception_index = TT_TFAULT;
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#ifdef DEBUG_MMU
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                printf("TFAULT at 0x%" PRIx64 "\n", address);
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#endif
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                DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n",
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                            address, context);
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                return 1;
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            }
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            *prot = PAGE_EXEC;
......
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            return 0;
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        }
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    }
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#ifdef DEBUG_MMU
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    printf("TMISS at 0x%" PRIx64 "\n", address);
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#endif
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    DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n",
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                address, context);
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    /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
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    env->immu.tag_access = (address & ~0x1fffULL) | context;
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    env->exception_index = TT_TMISS;
......
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        virt_addr = address & TARGET_PAGE_MASK;
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        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
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                             (TARGET_PAGE_SIZE - 1));
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#ifdef DEBUG_MMU
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        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
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               "\n", address, paddr, vaddr);
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#endif
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        DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 ","
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                    " vaddr %" PRIx64
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                    " mmu_idx=%d"
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                    " tl=%d"
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                    " primary context=%" PRIx64
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                    " secondary context=%" PRIx64
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                    "\n",
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                    address, paddr, vaddr, mmu_idx, env->tl,
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                    env->dmmu.mmu_primary_context,
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                    env->dmmu.mmu_secondary_context);
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        tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
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        return 0;
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    }

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