root / hw / pflash_cfi02.c @ b9055c3c
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/*
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* CFI parallel flash with AMD command set emulation
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*
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - chip erase
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* - unlock bypass command
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* - CFI queries
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*
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* It does not support flash interleaving.
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* It does not implement boot blocs with reduced size
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*/
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#include "hw.h" |
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#include "flash.h" |
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#include "qemu-timer.h" |
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#include "block.h" |
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|
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//#define PFLASH_DEBUG
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, ...) \
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do { \
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printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
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} while (0) |
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#else
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#define DPRINTF(fmt, ...) do { } while (0) |
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#endif
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|
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#define PFLASH_LAZY_ROMD_THRESHOLD 42 |
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|
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struct pflash_t {
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BlockDriverState *bs; |
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target_phys_addr_t base; |
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uint32_t sector_len; |
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uint32_t chip_len; |
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int mappings;
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int width;
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int wcycle; /* if 0, the flash is read normally */ |
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int bypass;
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int ro;
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uint8_t cmd; |
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uint8_t status; |
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uint16_t ident[4];
|
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uint16_t unlock_addr[2];
|
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uint8_t cfi_len; |
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uint8_t cfi_table[0x52];
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QEMUTimer *timer; |
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ram_addr_t off; |
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int fl_mem;
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int rom_mode;
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int read_counter; /* used for lazy switch-back to rom mode */ |
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void *storage;
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}; |
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|
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static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
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{
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unsigned long phys_offset = pfl->fl_mem; |
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int i;
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|
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if (rom_mode)
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phys_offset |= pfl->off | IO_MEM_ROMD; |
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pfl->rom_mode = rom_mode; |
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|
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for (i = 0; i < pfl->mappings; i++) |
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cpu_register_physical_memory(pfl->base + i * pfl->chip_len, |
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pfl->chip_len, phys_offset); |
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} |
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|
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static void pflash_timer (void *opaque) |
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{
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pflash_t *pfl = opaque; |
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|
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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pflash_register_memory(pfl, 1);
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pfl->wcycle = 0;
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} |
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pfl->cmd = 0;
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} |
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|
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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int width, int be) |
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{
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target_phys_addr_t boff; |
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uint32_t ret; |
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uint8_t *p; |
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|
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DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
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ret = -1;
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/* Lazy reset to ROMD mode after a certain amount of read accesses */
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if (!pfl->rom_mode && pfl->wcycle == 0 && |
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++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
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pflash_register_memory(pfl, 1);
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} |
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offset &= pfl->chip_len - 1;
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boff = offset & 0xFF;
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
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boff = boff >> 2;
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read*/
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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case 0x80: |
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/* We accept reads during second unlock sequence... */
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case 0x00: |
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flash_read:
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/* Flash area read */
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p = pfl->storage; |
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switch (width) {
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case 1: |
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ret = p[offset]; |
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// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2: |
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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} |
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// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4: |
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16; |
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ret |= p[offset + 2] << 8; |
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ret |= p[offset + 3];
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} else {
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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ret |= p[offset + 2] << 16; |
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ret |= p[offset + 3] << 24; |
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} |
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// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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} |
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break;
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case 0x90: |
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/* flash ID read */
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switch (boff) {
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case 0x00: |
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case 0x01: |
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ret = pfl->ident[boff & 0x01];
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break;
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case 0x02: |
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ret = 0x00; /* Pretend all sectors are unprotected */ |
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break;
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case 0x0E: |
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case 0x0F: |
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if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
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goto flash_read;
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ret = pfl->ident[2 + (boff & 0x01)]; |
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break;
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default:
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goto flash_read;
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} |
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DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); |
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break;
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case 0xA0: |
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case 0x10: |
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case 0x30: |
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/* Status register read */
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ret = pfl->status; |
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DPRINTF("%s: status %x\n", __func__, ret);
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/* Toggle bit 6 */
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pfl->status ^= 0x40;
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break;
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case 0x98: |
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/* CFI query mode */
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if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff]; |
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break;
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} |
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return ret;
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} |
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|
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset, |
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int size)
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{
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size; |
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/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9; |
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset); |
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} |
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} |
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static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, |
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uint32_t value, int width, int be) |
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{
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target_phys_addr_t boff; |
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uint8_t *p; |
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uint8_t cmd; |
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|
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cmd = value; |
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if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
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#if 0
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DPRINTF("%s: flash reset asked (%02x %02x)\n",
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__func__, pfl->cmd, cmd);
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#endif
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goto reset_flash;
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} |
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DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
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offset, value, width, pfl->wcycle); |
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offset &= pfl->chip_len - 1;
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|
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DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
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offset, value, width); |
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
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boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0: |
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/* Set the device in I/O access mode if required */
|
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if (pfl->rom_mode)
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pflash_register_memory(pfl, 0);
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pfl->read_counter = 0;
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/* We're in read mode */
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check_unlock0:
|
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if (boff == 0x55 && cmd == 0x98) { |
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enter_CFI_mode:
|
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/* Enter CFI query mode */
|
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pfl->wcycle = 7;
|
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pfl->cmd = 0x98;
|
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return;
|
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} |
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if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
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DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
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__func__, boff, cmd, pfl->unlock_addr[0]);
|
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goto reset_flash;
|
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} |
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DPRINTF("%s: unlock sequence started\n", __func__);
|
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break;
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case 1: |
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/* We started an unlock sequence */
|
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check_unlock1:
|
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if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
| 281 |
DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
| 282 |
boff, cmd); |
| 283 |
goto reset_flash;
|
| 284 |
} |
| 285 |
DPRINTF("%s: unlock sequence done\n", __func__);
|
| 286 |
break;
|
| 287 |
case 2: |
| 288 |
/* We finished an unlock sequence */
|
| 289 |
if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
| 290 |
DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
| 291 |
boff, cmd); |
| 292 |
goto reset_flash;
|
| 293 |
} |
| 294 |
switch (cmd) {
|
| 295 |
case 0x20: |
| 296 |
pfl->bypass = 1;
|
| 297 |
goto do_bypass;
|
| 298 |
case 0x80: |
| 299 |
case 0x90: |
| 300 |
case 0xA0: |
| 301 |
pfl->cmd = cmd; |
| 302 |
DPRINTF("%s: starting command %02x\n", __func__, cmd);
|
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break;
|
| 304 |
default:
|
| 305 |
DPRINTF("%s: unknown command %02x\n", __func__, cmd);
|
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goto reset_flash;
|
| 307 |
} |
| 308 |
break;
|
| 309 |
case 3: |
| 310 |
switch (pfl->cmd) {
|
| 311 |
case 0x80: |
| 312 |
/* We need another unlock sequence */
|
| 313 |
goto check_unlock0;
|
| 314 |
case 0xA0: |
| 315 |
DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
| 316 |
__func__, offset, value, width); |
| 317 |
p = pfl->storage; |
| 318 |
switch (width) {
|
| 319 |
case 1: |
| 320 |
p[offset] &= value; |
| 321 |
pflash_update(pfl, offset, 1);
|
| 322 |
break;
|
| 323 |
case 2: |
| 324 |
if (be) {
|
| 325 |
p[offset] &= value >> 8;
|
| 326 |
p[offset + 1] &= value;
|
| 327 |
} else {
|
| 328 |
p[offset] &= value; |
| 329 |
p[offset + 1] &= value >> 8; |
| 330 |
} |
| 331 |
pflash_update(pfl, offset, 2);
|
| 332 |
break;
|
| 333 |
case 4: |
| 334 |
if (be) {
|
| 335 |
p[offset] &= value >> 24;
|
| 336 |
p[offset + 1] &= value >> 16; |
| 337 |
p[offset + 2] &= value >> 8; |
| 338 |
p[offset + 3] &= value;
|
| 339 |
} else {
|
| 340 |
p[offset] &= value; |
| 341 |
p[offset + 1] &= value >> 8; |
| 342 |
p[offset + 2] &= value >> 16; |
| 343 |
p[offset + 3] &= value >> 24; |
| 344 |
} |
| 345 |
pflash_update(pfl, offset, 4);
|
| 346 |
break;
|
| 347 |
} |
| 348 |
pfl->status = 0x00 | ~(value & 0x80); |
| 349 |
/* Let's pretend write is immediate */
|
| 350 |
if (pfl->bypass)
|
| 351 |
goto do_bypass;
|
| 352 |
goto reset_flash;
|
| 353 |
case 0x90: |
| 354 |
if (pfl->bypass && cmd == 0x00) { |
| 355 |
/* Unlock bypass reset */
|
| 356 |
goto reset_flash;
|
| 357 |
} |
| 358 |
/* We can enter CFI query mode from autoselect mode */
|
| 359 |
if (boff == 0x55 && cmd == 0x98) |
| 360 |
goto enter_CFI_mode;
|
| 361 |
/* No break here */
|
| 362 |
default:
|
| 363 |
DPRINTF("%s: invalid write for command %02x\n",
|
| 364 |
__func__, pfl->cmd); |
| 365 |
goto reset_flash;
|
| 366 |
} |
| 367 |
case 4: |
| 368 |
switch (pfl->cmd) {
|
| 369 |
case 0xA0: |
| 370 |
/* Ignore writes while flash data write is occurring */
|
| 371 |
/* As we suppose write is immediate, this should never happen */
|
| 372 |
return;
|
| 373 |
case 0x80: |
| 374 |
goto check_unlock1;
|
| 375 |
default:
|
| 376 |
/* Should never happen */
|
| 377 |
DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
| 378 |
__func__, pfl->cmd); |
| 379 |
goto reset_flash;
|
| 380 |
} |
| 381 |
break;
|
| 382 |
case 5: |
| 383 |
switch (cmd) {
|
| 384 |
case 0x10: |
| 385 |
if (boff != pfl->unlock_addr[0]) { |
| 386 |
DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
| 387 |
__func__, offset); |
| 388 |
goto reset_flash;
|
| 389 |
} |
| 390 |
/* Chip erase */
|
| 391 |
DPRINTF("%s: start chip erase\n", __func__);
|
| 392 |
memset(pfl->storage, 0xFF, pfl->chip_len);
|
| 393 |
pfl->status = 0x00;
|
| 394 |
pflash_update(pfl, 0, pfl->chip_len);
|
| 395 |
/* Let's wait 5 seconds before chip erase is done */
|
| 396 |
qemu_mod_timer(pfl->timer, |
| 397 |
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
|
| 398 |
break;
|
| 399 |
case 0x30: |
| 400 |
/* Sector erase */
|
| 401 |
p = pfl->storage; |
| 402 |
offset &= ~(pfl->sector_len - 1);
|
| 403 |
DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
| 404 |
offset); |
| 405 |
memset(p + offset, 0xFF, pfl->sector_len);
|
| 406 |
pflash_update(pfl, offset, pfl->sector_len); |
| 407 |
pfl->status = 0x00;
|
| 408 |
/* Let's wait 1/2 second before sector erase is done */
|
| 409 |
qemu_mod_timer(pfl->timer, |
| 410 |
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
|
| 411 |
break;
|
| 412 |
default:
|
| 413 |
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
| 414 |
goto reset_flash;
|
| 415 |
} |
| 416 |
pfl->cmd = cmd; |
| 417 |
break;
|
| 418 |
case 6: |
| 419 |
switch (pfl->cmd) {
|
| 420 |
case 0x10: |
| 421 |
/* Ignore writes during chip erase */
|
| 422 |
return;
|
| 423 |
case 0x30: |
| 424 |
/* Ignore writes during sector erase */
|
| 425 |
return;
|
| 426 |
default:
|
| 427 |
/* Should never happen */
|
| 428 |
DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
| 429 |
__func__, pfl->cmd); |
| 430 |
goto reset_flash;
|
| 431 |
} |
| 432 |
break;
|
| 433 |
case 7: /* Special value for CFI queries */ |
| 434 |
DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
| 435 |
goto reset_flash;
|
| 436 |
default:
|
| 437 |
/* Should never happen */
|
| 438 |
DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
| 439 |
goto reset_flash;
|
| 440 |
} |
| 441 |
pfl->wcycle++; |
| 442 |
|
| 443 |
return;
|
| 444 |
|
| 445 |
/* Reset flash */
|
| 446 |
reset_flash:
|
| 447 |
pfl->bypass = 0;
|
| 448 |
pfl->wcycle = 0;
|
| 449 |
pfl->cmd = 0;
|
| 450 |
return;
|
| 451 |
|
| 452 |
do_bypass:
|
| 453 |
pfl->wcycle = 2;
|
| 454 |
pfl->cmd = 0;
|
| 455 |
return;
|
| 456 |
} |
| 457 |
|
| 458 |
|
| 459 |
static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) |
| 460 |
{
|
| 461 |
return pflash_read(opaque, addr, 1, 1); |
| 462 |
} |
| 463 |
|
| 464 |
static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) |
| 465 |
{
|
| 466 |
return pflash_read(opaque, addr, 1, 0); |
| 467 |
} |
| 468 |
|
| 469 |
static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) |
| 470 |
{
|
| 471 |
pflash_t *pfl = opaque; |
| 472 |
|
| 473 |
return pflash_read(pfl, addr, 2, 1); |
| 474 |
} |
| 475 |
|
| 476 |
static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) |
| 477 |
{
|
| 478 |
pflash_t *pfl = opaque; |
| 479 |
|
| 480 |
return pflash_read(pfl, addr, 2, 0); |
| 481 |
} |
| 482 |
|
| 483 |
static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) |
| 484 |
{
|
| 485 |
pflash_t *pfl = opaque; |
| 486 |
|
| 487 |
return pflash_read(pfl, addr, 4, 1); |
| 488 |
} |
| 489 |
|
| 490 |
static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) |
| 491 |
{
|
| 492 |
pflash_t *pfl = opaque; |
| 493 |
|
| 494 |
return pflash_read(pfl, addr, 4, 0); |
| 495 |
} |
| 496 |
|
| 497 |
static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, |
| 498 |
uint32_t value) |
| 499 |
{
|
| 500 |
pflash_write(opaque, addr, value, 1, 1); |
| 501 |
} |
| 502 |
|
| 503 |
static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, |
| 504 |
uint32_t value) |
| 505 |
{
|
| 506 |
pflash_write(opaque, addr, value, 1, 0); |
| 507 |
} |
| 508 |
|
| 509 |
static void pflash_writew_be(void *opaque, target_phys_addr_t addr, |
| 510 |
uint32_t value) |
| 511 |
{
|
| 512 |
pflash_t *pfl = opaque; |
| 513 |
|
| 514 |
pflash_write(pfl, addr, value, 2, 1); |
| 515 |
} |
| 516 |
|
| 517 |
static void pflash_writew_le(void *opaque, target_phys_addr_t addr, |
| 518 |
uint32_t value) |
| 519 |
{
|
| 520 |
pflash_t *pfl = opaque; |
| 521 |
|
| 522 |
pflash_write(pfl, addr, value, 2, 0); |
| 523 |
} |
| 524 |
|
| 525 |
static void pflash_writel_be(void *opaque, target_phys_addr_t addr, |
| 526 |
uint32_t value) |
| 527 |
{
|
| 528 |
pflash_t *pfl = opaque; |
| 529 |
|
| 530 |
pflash_write(pfl, addr, value, 4, 1); |
| 531 |
} |
| 532 |
|
| 533 |
static void pflash_writel_le(void *opaque, target_phys_addr_t addr, |
| 534 |
uint32_t value) |
| 535 |
{
|
| 536 |
pflash_t *pfl = opaque; |
| 537 |
|
| 538 |
pflash_write(pfl, addr, value, 4, 0); |
| 539 |
} |
| 540 |
|
| 541 |
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { |
| 542 |
&pflash_writeb_be, |
| 543 |
&pflash_writew_be, |
| 544 |
&pflash_writel_be, |
| 545 |
}; |
| 546 |
|
| 547 |
static CPUReadMemoryFunc * const pflash_read_ops_be[] = { |
| 548 |
&pflash_readb_be, |
| 549 |
&pflash_readw_be, |
| 550 |
&pflash_readl_be, |
| 551 |
}; |
| 552 |
|
| 553 |
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = { |
| 554 |
&pflash_writeb_le, |
| 555 |
&pflash_writew_le, |
| 556 |
&pflash_writel_le, |
| 557 |
}; |
| 558 |
|
| 559 |
static CPUReadMemoryFunc * const pflash_read_ops_le[] = { |
| 560 |
&pflash_readb_le, |
| 561 |
&pflash_readw_le, |
| 562 |
&pflash_readl_le, |
| 563 |
}; |
| 564 |
|
| 565 |
/* Count trailing zeroes of a 32 bits quantity */
|
| 566 |
static int ctz32 (uint32_t n) |
| 567 |
{
|
| 568 |
int ret;
|
| 569 |
|
| 570 |
ret = 0;
|
| 571 |
if (!(n & 0xFFFF)) { |
| 572 |
ret += 16;
|
| 573 |
n = n >> 16;
|
| 574 |
} |
| 575 |
if (!(n & 0xFF)) { |
| 576 |
ret += 8;
|
| 577 |
n = n >> 8;
|
| 578 |
} |
| 579 |
if (!(n & 0xF)) { |
| 580 |
ret += 4;
|
| 581 |
n = n >> 4;
|
| 582 |
} |
| 583 |
if (!(n & 0x3)) { |
| 584 |
ret += 2;
|
| 585 |
n = n >> 2;
|
| 586 |
} |
| 587 |
if (!(n & 0x1)) { |
| 588 |
ret++; |
| 589 |
#if 0 /* This is not necessary as n is never 0 */
|
| 590 |
n = n >> 1;
|
| 591 |
#endif
|
| 592 |
} |
| 593 |
#if 0 /* This is not necessary as n is never 0 */
|
| 594 |
if (!n)
|
| 595 |
ret++;
|
| 596 |
#endif
|
| 597 |
|
| 598 |
return ret;
|
| 599 |
} |
| 600 |
|
| 601 |
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
| 602 |
BlockDriverState *bs, uint32_t sector_len, |
| 603 |
int nb_blocs, int nb_mappings, int width, |
| 604 |
uint16_t id0, uint16_t id1, |
| 605 |
uint16_t id2, uint16_t id3, |
| 606 |
uint16_t unlock_addr0, uint16_t unlock_addr1, |
| 607 |
int be)
|
| 608 |
{
|
| 609 |
pflash_t *pfl; |
| 610 |
int32_t chip_len; |
| 611 |
int ret;
|
| 612 |
|
| 613 |
chip_len = sector_len * nb_blocs; |
| 614 |
/* XXX: to be fixed */
|
| 615 |
#if 0
|
| 616 |
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
| 617 |
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
| 618 |
return NULL;
|
| 619 |
#endif
|
| 620 |
pfl = qemu_mallocz(sizeof(pflash_t));
|
| 621 |
/* FIXME: Allocate ram ourselves. */
|
| 622 |
pfl->storage = qemu_get_ram_ptr(off); |
| 623 |
if (be) {
|
| 624 |
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, |
| 625 |
pflash_write_ops_be, |
| 626 |
pfl, DEVICE_NATIVE_ENDIAN); |
| 627 |
} else {
|
| 628 |
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, |
| 629 |
pflash_write_ops_le, |
| 630 |
pfl, DEVICE_NATIVE_ENDIAN); |
| 631 |
} |
| 632 |
pfl->off = off; |
| 633 |
pfl->base = base; |
| 634 |
pfl->chip_len = chip_len; |
| 635 |
pfl->mappings = nb_mappings; |
| 636 |
pflash_register_memory(pfl, 1);
|
| 637 |
pfl->bs = bs; |
| 638 |
if (pfl->bs) {
|
| 639 |
/* read the initial flash content */
|
| 640 |
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
| 641 |
if (ret < 0) { |
| 642 |
cpu_unregister_io_memory(pfl->fl_mem); |
| 643 |
qemu_free(pfl); |
| 644 |
return NULL; |
| 645 |
} |
| 646 |
} |
| 647 |
#if 0 /* XXX: there should be a bit to set up read-only,
|
| 648 |
* the same way the hardware does (with WP pin).
|
| 649 |
*/
|
| 650 |
pfl->ro = 1;
|
| 651 |
#else
|
| 652 |
pfl->ro = 0;
|
| 653 |
#endif
|
| 654 |
pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
| 655 |
pfl->sector_len = sector_len; |
| 656 |
pfl->width = width; |
| 657 |
pfl->wcycle = 0;
|
| 658 |
pfl->cmd = 0;
|
| 659 |
pfl->status = 0;
|
| 660 |
pfl->ident[0] = id0;
|
| 661 |
pfl->ident[1] = id1;
|
| 662 |
pfl->ident[2] = id2;
|
| 663 |
pfl->ident[3] = id3;
|
| 664 |
pfl->unlock_addr[0] = unlock_addr0;
|
| 665 |
pfl->unlock_addr[1] = unlock_addr1;
|
| 666 |
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
| 667 |
pfl->cfi_len = 0x52;
|
| 668 |
/* Standard "QRY" string */
|
| 669 |
pfl->cfi_table[0x10] = 'Q'; |
| 670 |
pfl->cfi_table[0x11] = 'R'; |
| 671 |
pfl->cfi_table[0x12] = 'Y'; |
| 672 |
/* Command set (AMD/Fujitsu) */
|
| 673 |
pfl->cfi_table[0x13] = 0x02; |
| 674 |
pfl->cfi_table[0x14] = 0x00; |
| 675 |
/* Primary extended table address */
|
| 676 |
pfl->cfi_table[0x15] = 0x31; |
| 677 |
pfl->cfi_table[0x16] = 0x00; |
| 678 |
/* Alternate command set (none) */
|
| 679 |
pfl->cfi_table[0x17] = 0x00; |
| 680 |
pfl->cfi_table[0x18] = 0x00; |
| 681 |
/* Alternate extended table (none) */
|
| 682 |
pfl->cfi_table[0x19] = 0x00; |
| 683 |
pfl->cfi_table[0x1A] = 0x00; |
| 684 |
/* Vcc min */
|
| 685 |
pfl->cfi_table[0x1B] = 0x27; |
| 686 |
/* Vcc max */
|
| 687 |
pfl->cfi_table[0x1C] = 0x36; |
| 688 |
/* Vpp min (no Vpp pin) */
|
| 689 |
pfl->cfi_table[0x1D] = 0x00; |
| 690 |
/* Vpp max (no Vpp pin) */
|
| 691 |
pfl->cfi_table[0x1E] = 0x00; |
| 692 |
/* Reserved */
|
| 693 |
pfl->cfi_table[0x1F] = 0x07; |
| 694 |
/* Timeout for min size buffer write (NA) */
|
| 695 |
pfl->cfi_table[0x20] = 0x00; |
| 696 |
/* Typical timeout for block erase (512 ms) */
|
| 697 |
pfl->cfi_table[0x21] = 0x09; |
| 698 |
/* Typical timeout for full chip erase (4096 ms) */
|
| 699 |
pfl->cfi_table[0x22] = 0x0C; |
| 700 |
/* Reserved */
|
| 701 |
pfl->cfi_table[0x23] = 0x01; |
| 702 |
/* Max timeout for buffer write (NA) */
|
| 703 |
pfl->cfi_table[0x24] = 0x00; |
| 704 |
/* Max timeout for block erase */
|
| 705 |
pfl->cfi_table[0x25] = 0x0A; |
| 706 |
/* Max timeout for chip erase */
|
| 707 |
pfl->cfi_table[0x26] = 0x0D; |
| 708 |
/* Device size */
|
| 709 |
pfl->cfi_table[0x27] = ctz32(chip_len);
|
| 710 |
/* Flash device interface (8 & 16 bits) */
|
| 711 |
pfl->cfi_table[0x28] = 0x02; |
| 712 |
pfl->cfi_table[0x29] = 0x00; |
| 713 |
/* Max number of bytes in multi-bytes write */
|
| 714 |
/* XXX: disable buffered write as it's not supported */
|
| 715 |
// pfl->cfi_table[0x2A] = 0x05;
|
| 716 |
pfl->cfi_table[0x2A] = 0x00; |
| 717 |
pfl->cfi_table[0x2B] = 0x00; |
| 718 |
/* Number of erase block regions (uniform) */
|
| 719 |
pfl->cfi_table[0x2C] = 0x01; |
| 720 |
/* Erase block region 1 */
|
| 721 |
pfl->cfi_table[0x2D] = nb_blocs - 1; |
| 722 |
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
| 723 |
pfl->cfi_table[0x2F] = sector_len >> 8; |
| 724 |
pfl->cfi_table[0x30] = sector_len >> 16; |
| 725 |
|
| 726 |
/* Extended */
|
| 727 |
pfl->cfi_table[0x31] = 'P'; |
| 728 |
pfl->cfi_table[0x32] = 'R'; |
| 729 |
pfl->cfi_table[0x33] = 'I'; |
| 730 |
|
| 731 |
pfl->cfi_table[0x34] = '1'; |
| 732 |
pfl->cfi_table[0x35] = '0'; |
| 733 |
|
| 734 |
pfl->cfi_table[0x36] = 0x00; |
| 735 |
pfl->cfi_table[0x37] = 0x00; |
| 736 |
pfl->cfi_table[0x38] = 0x00; |
| 737 |
pfl->cfi_table[0x39] = 0x00; |
| 738 |
|
| 739 |
pfl->cfi_table[0x3a] = 0x00; |
| 740 |
|
| 741 |
pfl->cfi_table[0x3b] = 0x00; |
| 742 |
pfl->cfi_table[0x3c] = 0x00; |
| 743 |
|
| 744 |
return pfl;
|
| 745 |
} |