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/*
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 * QEMU System Emulator header
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd, 
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                         IOCanRWHandler *fd_read_poll, 
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                         IOHandler *fd_read, 
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                         IOHandler *fd_write, 
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read, 
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s, 
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                           IOCanRWHandler *fd_can_read, 
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
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    void *buffer;
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    int count;
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};
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
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    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
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       rate-limit the slirp code.  */
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    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
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    struct VLANState *vlan;
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    char info_str[256];
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};
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typedef struct VLANState {
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    int id;
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    VLANClientState *first_client;
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    struct VLANState *next;
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} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
388 d861b05e pbrook
                                      IOReadHandler *fd_read,
389 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
390 d861b05e pbrook
                                      void *opaque);
391 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
392 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
393 d861b05e pbrook
void qemu_handler_true(void *opaque);
394 7c9d8e07 bellard
395 7c9d8e07 bellard
void do_info_network(void);
396 7c9d8e07 bellard
397 7fb843f8 bellard
/* TAP win32 */
398 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
399 7fb843f8 bellard
400 7c9d8e07 bellard
/* NIC info */
401 c4b1fcc0 bellard
402 c4b1fcc0 bellard
#define MAX_NICS 8
403 c4b1fcc0 bellard
404 7c9d8e07 bellard
typedef struct NICInfo {
405 c4b1fcc0 bellard
    uint8_t macaddr[6];
406 a41b2ff2 pbrook
    const char *model;
407 7c9d8e07 bellard
    VLANState *vlan;
408 7c9d8e07 bellard
} NICInfo;
409 c4b1fcc0 bellard
410 c4b1fcc0 bellard
extern int nb_nics;
411 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
412 8a7ddc38 bellard
413 8a7ddc38 bellard
/* timers */
414 8a7ddc38 bellard
415 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
416 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
417 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
418 8a7ddc38 bellard
419 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
420 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
421 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
422 8a7ddc38 bellard
   Hz. */
423 8a7ddc38 bellard
extern QEMUClock *rt_clock;
424 8a7ddc38 bellard
425 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
426 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
427 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
428 8a7ddc38 bellard
extern QEMUClock *vm_clock;
429 8a7ddc38 bellard
430 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
431 8a7ddc38 bellard
432 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
433 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
434 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
435 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
436 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
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438 8a7ddc38 bellard
extern int64_t ticks_per_sec;
439 8a7ddc38 bellard
extern int pit_min_timer_count;
440 8a7ddc38 bellard
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int64_t cpu_get_ticks(void);
442 8a7ddc38 bellard
void cpu_enable_ticks(void);
443 8a7ddc38 bellard
void cpu_disable_ticks(void);
444 8a7ddc38 bellard
445 8a7ddc38 bellard
/* VM Load/Save */
446 8a7ddc38 bellard
447 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
448 8a7ddc38 bellard
449 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
450 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
451 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
452 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
453 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
454 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
455 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
456 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
457 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
458 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
459 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
460 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
461 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
462 8a7ddc38 bellard
463 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
464 8a7ddc38 bellard
{
465 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
466 8a7ddc38 bellard
}
467 8a7ddc38 bellard
468 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
469 8a7ddc38 bellard
{
470 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
471 8a7ddc38 bellard
}
472 8a7ddc38 bellard
473 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
474 8a7ddc38 bellard
{
475 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
476 8a7ddc38 bellard
}
477 8a7ddc38 bellard
478 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
479 8a7ddc38 bellard
{
480 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
481 8a7ddc38 bellard
}
482 8a7ddc38 bellard
483 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
484 8a7ddc38 bellard
{
485 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
486 8a7ddc38 bellard
}
487 8a7ddc38 bellard
488 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
489 8a7ddc38 bellard
{
490 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
491 8a7ddc38 bellard
}
492 8a7ddc38 bellard
493 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
494 8a7ddc38 bellard
{
495 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
496 8a7ddc38 bellard
}
497 8a7ddc38 bellard
498 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
499 8a7ddc38 bellard
{
500 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
501 8a7ddc38 bellard
}
502 8a7ddc38 bellard
503 c27004ec bellard
#if TARGET_LONG_BITS == 64
504 c27004ec bellard
#define qemu_put_betl qemu_put_be64
505 c27004ec bellard
#define qemu_get_betl qemu_get_be64
506 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
507 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
508 c27004ec bellard
#else
509 c27004ec bellard
#define qemu_put_betl qemu_put_be32
510 c27004ec bellard
#define qemu_get_betl qemu_get_be32
511 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
512 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
513 c27004ec bellard
#endif
514 c27004ec bellard
515 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
516 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
517 8a7ddc38 bellard
518 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
519 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
520 8a7ddc38 bellard
521 8a7ddc38 bellard
int register_savevm(const char *idstr, 
522 8a7ddc38 bellard
                    int instance_id, 
523 8a7ddc38 bellard
                    int version_id,
524 8a7ddc38 bellard
                    SaveStateHandler *save_state,
525 8a7ddc38 bellard
                    LoadStateHandler *load_state,
526 8a7ddc38 bellard
                    void *opaque);
527 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
528 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
529 c4b1fcc0 bellard
530 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
531 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
532 6a00d601 bellard
533 faea38e7 bellard
void do_savevm(const char *name);
534 faea38e7 bellard
void do_loadvm(const char *name);
535 faea38e7 bellard
void do_delvm(const char *name);
536 faea38e7 bellard
void do_info_snapshots(void);
537 faea38e7 bellard
538 83f64091 bellard
/* bottom halves */
539 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
540 83f64091 bellard
541 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
542 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
543 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
544 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
545 6eb5733a bellard
int qemu_bh_poll(void);
546 83f64091 bellard
547 fc01f7e7 bellard
/* block.c */
548 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
549 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
550 ea2384d3 bellard
551 ea2384d3 bellard
extern BlockDriver bdrv_raw;
552 19cb3738 bellard
extern BlockDriver bdrv_host_device;
553 ea2384d3 bellard
extern BlockDriver bdrv_cow;
554 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
555 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
556 3c56521b bellard
extern BlockDriver bdrv_cloop;
557 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
558 a8753c34 bellard
extern BlockDriver bdrv_bochs;
559 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
560 de167e41 bellard
extern BlockDriver bdrv_vvfat;
561 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
562 faea38e7 bellard
563 faea38e7 bellard
typedef struct BlockDriverInfo {
564 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
565 faea38e7 bellard
    int cluster_size; 
566 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
567 faea38e7 bellard
    int64_t vm_state_offset; 
568 faea38e7 bellard
} BlockDriverInfo;
569 faea38e7 bellard
570 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
571 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
572 faea38e7 bellard
    /* the following fields are informative. They are not needed for
573 faea38e7 bellard
       the consistency of the snapshot */
574 faea38e7 bellard
    char name[256]; /* user choosen name */
575 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
576 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
577 faea38e7 bellard
    uint32_t date_nsec;
578 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
579 faea38e7 bellard
} QEMUSnapshotInfo;
580 ea2384d3 bellard
581 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
582 83f64091 bellard
#define BDRV_O_RDWR        0x0002
583 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
584 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
585 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
586 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
587 83f64091 bellard
                                     use a disk image format on top of
588 83f64091 bellard
                                     it (default for
589 83f64091 bellard
                                     bdrv_file_open()) */
590 83f64091 bellard
591 ea2384d3 bellard
void bdrv_init(void);
592 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
593 ea2384d3 bellard
int bdrv_create(BlockDriver *drv, 
594 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
595 ea2384d3 bellard
                const char *backing_file, int flags);
596 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
597 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
598 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
599 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
600 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
601 ea2384d3 bellard
               BlockDriver *drv);
602 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
603 fc01f7e7 bellard
int bdrv_read(BlockDriverState *bs, int64_t sector_num, 
604 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
605 fc01f7e7 bellard
int bdrv_write(BlockDriverState *bs, int64_t sector_num, 
606 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
607 83f64091 bellard
int bdrv_pread(BlockDriverState *bs, int64_t offset, 
608 83f64091 bellard
               void *buf, int count);
609 83f64091 bellard
int bdrv_pwrite(BlockDriverState *bs, int64_t offset, 
610 83f64091 bellard
                const void *buf, int count);
611 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
612 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
613 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
614 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
615 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
616 83f64091 bellard
/* async block I/O */
617 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
618 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
619 83f64091 bellard
620 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
621 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
622 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
623 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
624 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
625 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
626 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
627 83f64091 bellard
628 83f64091 bellard
void qemu_aio_init(void);
629 83f64091 bellard
void qemu_aio_poll(void);
630 6192bc37 pbrook
void qemu_aio_flush(void);
631 83f64091 bellard
void qemu_aio_wait_start(void);
632 83f64091 bellard
void qemu_aio_wait(void);
633 83f64091 bellard
void qemu_aio_wait_end(void);
634 83f64091 bellard
635 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
636 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
637 33e3963e bellard
638 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
639 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
640 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
641 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
642 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
643 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
644 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
645 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
646 c4b1fcc0 bellard
647 c4b1fcc0 bellard
void bdrv_set_geometry_hint(BlockDriverState *bs, 
648 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
649 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
650 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
651 c4b1fcc0 bellard
void bdrv_get_geometry_hint(BlockDriverState *bs, 
652 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
653 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
654 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
655 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
656 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
657 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
658 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
659 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
660 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
661 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
662 c4b1fcc0 bellard
void bdrv_set_change_cb(BlockDriverState *bs, 
663 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
664 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
665 c4b1fcc0 bellard
void bdrv_info(void);
666 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
667 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
668 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
669 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
670 ea2384d3 bellard
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), 
671 ea2384d3 bellard
                         void *opaque);
672 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
673 faea38e7 bellard
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num, 
674 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
675 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
676 c4b1fcc0 bellard
677 83f64091 bellard
void bdrv_get_backing_filename(BlockDriverState *bs, 
678 83f64091 bellard
                               char *filename, int filename_size);
679 faea38e7 bellard
int bdrv_snapshot_create(BlockDriverState *bs, 
680 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
681 faea38e7 bellard
int bdrv_snapshot_goto(BlockDriverState *bs, 
682 faea38e7 bellard
                       const char *snapshot_id);
683 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
684 faea38e7 bellard
int bdrv_snapshot_list(BlockDriverState *bs, 
685 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
686 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
687 faea38e7 bellard
688 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
689 83f64091 bellard
int path_is_absolute(const char *path);
690 83f64091 bellard
void path_combine(char *dest, int dest_size,
691 83f64091 bellard
                  const char *base_path,
692 83f64091 bellard
                  const char *filename);
693 ea2384d3 bellard
694 ea2384d3 bellard
#ifndef QEMU_TOOL
695 54fa5af5 bellard
696 54fa5af5 bellard
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, 
697 54fa5af5 bellard
                                 int boot_device,
698 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
699 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
700 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
701 54fa5af5 bellard
702 54fa5af5 bellard
typedef struct QEMUMachine {
703 54fa5af5 bellard
    const char *name;
704 54fa5af5 bellard
    const char *desc;
705 54fa5af5 bellard
    QEMUMachineInitFunc *init;
706 54fa5af5 bellard
    struct QEMUMachine *next;
707 54fa5af5 bellard
} QEMUMachine;
708 54fa5af5 bellard
709 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
710 54fa5af5 bellard
711 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
712 54fa5af5 bellard
713 94fc95cd j_mayer
#if defined(TARGET_PPC)
714 94fc95cd j_mayer
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
715 94fc95cd j_mayer
#endif
716 94fc95cd j_mayer
717 33d68b5f ths
#if defined(TARGET_MIPS)
718 33d68b5f ths
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
719 33d68b5f ths
#endif
720 33d68b5f ths
721 d537cf6c pbrook
#include "hw/irq.h"
722 d537cf6c pbrook
723 26aa7d72 bellard
/* ISA bus */
724 26aa7d72 bellard
725 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
726 26aa7d72 bellard
727 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
728 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
729 26aa7d72 bellard
730 26aa7d72 bellard
int register_ioport_read(int start, int length, int size, 
731 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
732 26aa7d72 bellard
int register_ioport_write(int start, int length, int size, 
733 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
734 69b91039 bellard
void isa_unassign_ioport(int start, int length);
735 69b91039 bellard
736 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
737 aef445bd pbrook
738 69b91039 bellard
/* PCI bus */
739 69b91039 bellard
740 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
741 69b91039 bellard
742 46e50e9d bellard
typedef struct PCIBus PCIBus;
743 69b91039 bellard
typedef struct PCIDevice PCIDevice;
744 69b91039 bellard
745 69b91039 bellard
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 
746 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
747 69b91039 bellard
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 
748 69b91039 bellard
                                   uint32_t address, int len);
749 69b91039 bellard
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 
750 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
751 69b91039 bellard
752 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
753 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
754 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
755 69b91039 bellard
756 69b91039 bellard
typedef struct PCIIORegion {
757 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
758 69b91039 bellard
    uint32_t size;
759 69b91039 bellard
    uint8_t type;
760 69b91039 bellard
    PCIMapIORegionFunc *map_func;
761 69b91039 bellard
} PCIIORegion;
762 69b91039 bellard
763 8a8696a3 bellard
#define PCI_ROM_SLOT 6
764 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
765 502a5395 pbrook
766 502a5395 pbrook
#define PCI_DEVICES_MAX 64
767 502a5395 pbrook
768 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
769 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
770 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
771 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
772 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
773 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
774 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
775 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
776 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
777 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
778 502a5395 pbrook
779 69b91039 bellard
struct PCIDevice {
780 69b91039 bellard
    /* PCI config space */
781 69b91039 bellard
    uint8_t config[256];
782 69b91039 bellard
783 69b91039 bellard
    /* the following fields are read only */
784 46e50e9d bellard
    PCIBus *bus;
785 69b91039 bellard
    int devfn;
786 69b91039 bellard
    char name[64];
787 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
788 69b91039 bellard
    
789 69b91039 bellard
    /* do not access the following fields */
790 69b91039 bellard
    PCIConfigReadFunc *config_read;
791 69b91039 bellard
    PCIConfigWriteFunc *config_write;
792 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
793 5768f5ac bellard
    int irq_index;
794 d2b59317 pbrook
795 d537cf6c pbrook
    /* IRQ objects for the INTA-INTD pins.  */
796 d537cf6c pbrook
    qemu_irq *irq;
797 d537cf6c pbrook
798 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
799 d2b59317 pbrook
    int irq_state[4];
800 69b91039 bellard
};
801 69b91039 bellard
802 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
803 46e50e9d bellard
                               int instance_size, int devfn,
804 69b91039 bellard
                               PCIConfigReadFunc *config_read, 
805 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
806 69b91039 bellard
807 69b91039 bellard
void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
808 69b91039 bellard
                            uint32_t size, int type, 
809 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
810 69b91039 bellard
811 5768f5ac bellard
uint32_t pci_default_read_config(PCIDevice *d, 
812 5768f5ac bellard
                                 uint32_t address, int len);
813 5768f5ac bellard
void pci_default_write_config(PCIDevice *d, 
814 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
815 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
816 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
817 5768f5ac bellard
818 d537cf6c pbrook
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
819 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
820 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
821 d537cf6c pbrook
                         qemu_irq *pic, int devfn_min, int nirq);
822 502a5395 pbrook
823 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
824 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
825 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
826 502a5395 pbrook
int pci_bus_num(PCIBus *s);
827 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
828 9995c51f bellard
829 5768f5ac bellard
void pci_info(void);
830 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
831 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
832 26aa7d72 bellard
833 502a5395 pbrook
/* prep_pci.c */
834 d537cf6c pbrook
PCIBus *pci_prep_init(qemu_irq *pic);
835 77d4bc34 bellard
836 502a5395 pbrook
/* grackle_pci.c */
837 d537cf6c pbrook
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
838 502a5395 pbrook
839 502a5395 pbrook
/* unin_pci.c */
840 d537cf6c pbrook
PCIBus *pci_pmac_init(qemu_irq *pic);
841 502a5395 pbrook
842 502a5395 pbrook
/* apb_pci.c */
843 502a5395 pbrook
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
844 d537cf6c pbrook
                     qemu_irq *pic);
845 502a5395 pbrook
846 d537cf6c pbrook
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
847 502a5395 pbrook
848 502a5395 pbrook
/* piix_pci.c */
849 d537cf6c pbrook
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
850 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
851 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
852 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
853 a41b2ff2 pbrook
854 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
855 5856de80 ths
856 28b9b5af bellard
/* openpic.c */
857 e9df014c j_mayer
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
858 47103572 j_mayer
enum {
859 e9df014c j_mayer
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
860 e9df014c j_mayer
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
861 e9df014c j_mayer
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
862 e9df014c j_mayer
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
863 e9df014c j_mayer
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
864 e9df014c j_mayer
    OPENPIC_OUTPUT_NB,
865 47103572 j_mayer
};
866 e9df014c j_mayer
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
867 e9df014c j_mayer
                        qemu_irq **irqs, qemu_irq irq_out);
868 28b9b5af bellard
869 54fa5af5 bellard
/* heathrow_pic.c */
870 d537cf6c pbrook
qemu_irq *heathrow_pic_init(int *pmem_index);
871 54fa5af5 bellard
872 fde7d5bd ths
/* gt64xxx.c */
873 d537cf6c pbrook
PCIBus *pci_gt64120_init(qemu_irq *pic);
874 fde7d5bd ths
875 6a36d84e bellard
#ifdef HAS_AUDIO
876 6a36d84e bellard
struct soundhw {
877 6a36d84e bellard
    const char *name;
878 6a36d84e bellard
    const char *descr;
879 6a36d84e bellard
    int enabled;
880 6a36d84e bellard
    int isa;
881 6a36d84e bellard
    union {
882 d537cf6c pbrook
        int (*init_isa) (AudioState *s, qemu_irq *pic);
883 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
884 6a36d84e bellard
    } init;
885 6a36d84e bellard
};
886 6a36d84e bellard
887 6a36d84e bellard
extern struct soundhw soundhw[];
888 6a36d84e bellard
#endif
889 6a36d84e bellard
890 313aa567 bellard
/* vga.c */
891 313aa567 bellard
892 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
893 313aa567 bellard
894 82c643ff bellard
struct DisplayState {
895 313aa567 bellard
    uint8_t *data;
896 313aa567 bellard
    int linesize;
897 313aa567 bellard
    int depth;
898 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
899 82c643ff bellard
    int width;
900 82c643ff bellard
    int height;
901 24236869 bellard
    void *opaque;
902 24236869 bellard
903 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
904 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
905 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
906 d34cab9f ths
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
907 d34cab9f ths
                     int dst_x, int dst_y, int w, int h);
908 d34cab9f ths
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
909 d34cab9f ths
                     int w, int h, uint32_t c);
910 d34cab9f ths
    void (*mouse_set)(int x, int y, int on);
911 d34cab9f ths
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
912 d34cab9f ths
                          uint8_t *image, uint8_t *mask);
913 82c643ff bellard
};
914 313aa567 bellard
915 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
916 313aa567 bellard
{
917 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
918 313aa567 bellard
}
919 313aa567 bellard
920 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
921 313aa567 bellard
{
922 313aa567 bellard
    s->dpy_resize(s, w, h);
923 313aa567 bellard
}
924 313aa567 bellard
925 89b6b508 bellard
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
926 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
927 89b6b508 bellard
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
928 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
929 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
930 313aa567 bellard
931 d6bfa22f bellard
/* cirrus_vga.c */
932 46e50e9d bellard
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
933 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
934 d6bfa22f bellard
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
935 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
936 d6bfa22f bellard
937 d34cab9f ths
/* vmware_vga.c */
938 d34cab9f ths
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
939 d34cab9f ths
                     unsigned long vga_ram_offset, int vga_ram_size);
940 d34cab9f ths
941 313aa567 bellard
/* sdl.c */
942 43523e93 ths
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
943 313aa567 bellard
944 da4dbf74 bellard
/* cocoa.m */
945 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
946 da4dbf74 bellard
947 24236869 bellard
/* vnc.c */
948 73fc9742 ths
void vnc_display_init(DisplayState *ds, const char *display);
949 a9ce8590 bellard
void do_info_vnc(void);
950 24236869 bellard
951 6070dd07 ths
/* x_keymap.c */
952 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
953 6070dd07 ths
954 5391d806 bellard
/* ide.c */
955 5391d806 bellard
#define MAX_DISKS 4
956 5391d806 bellard
957 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
958 a1bb27b1 pbrook
extern BlockDriverState *sd_bdrv;
959 5391d806 bellard
960 d537cf6c pbrook
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
961 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
962 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
963 54fa5af5 bellard
                         int secondary_ide_enabled);
964 d537cf6c pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
965 d537cf6c pbrook
                        qemu_irq *pic);
966 d537cf6c pbrook
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
967 5391d806 bellard
968 2e5d83bb pbrook
/* cdrom.c */
969 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
970 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
971 2e5d83bb pbrook
972 9542611a ths
/* ds1225y.c */
973 9542611a ths
typedef struct ds1225y_t ds1225y_t;
974 9542611a ths
ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
975 9542611a ths
976 1d14ffa9 bellard
/* es1370.c */
977 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
978 1d14ffa9 bellard
979 fb065187 bellard
/* sb16.c */
980 d537cf6c pbrook
int SB16_init (AudioState *s, qemu_irq *pic);
981 fb065187 bellard
982 fb065187 bellard
/* adlib.c */
983 d537cf6c pbrook
int Adlib_init (AudioState *s, qemu_irq *pic);
984 fb065187 bellard
985 fb065187 bellard
/* gus.c */
986 d537cf6c pbrook
int GUS_init (AudioState *s, qemu_irq *pic);
987 27503323 bellard
988 27503323 bellard
/* dma.c */
989 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
990 27503323 bellard
int DMA_get_channel_mode (int nchan);
991 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
992 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
993 27503323 bellard
void DMA_hold_DREQ (int nchan);
994 27503323 bellard
void DMA_release_DREQ (int nchan);
995 16f62432 bellard
void DMA_schedule(int nchan);
996 27503323 bellard
void DMA_run (void);
997 28b9b5af bellard
void DMA_init (int high_page_enable);
998 27503323 bellard
void DMA_register_channel (int nchan,
999 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
1000 85571bc7 bellard
                           void *opaque);
1001 7138fcfb bellard
/* fdc.c */
1002 7138fcfb bellard
#define MAX_FD 2
1003 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
1004 7138fcfb bellard
1005 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
1006 baca51fa bellard
1007 d537cf6c pbrook
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, 
1008 baca51fa bellard
                       uint32_t io_base,
1009 baca51fa bellard
                       BlockDriverState **fds);
1010 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1011 7138fcfb bellard
1012 663e8e51 ths
/* eepro100.c */
1013 663e8e51 ths
1014 663e8e51 ths
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1015 663e8e51 ths
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1016 663e8e51 ths
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1017 663e8e51 ths
1018 80cabfad bellard
/* ne2000.c */
1019 80cabfad bellard
1020 d537cf6c pbrook
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1021 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1022 80cabfad bellard
1023 a41b2ff2 pbrook
/* rtl8139.c */
1024 a41b2ff2 pbrook
1025 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1026 a41b2ff2 pbrook
1027 e3c2613f bellard
/* pcnet.c */
1028 e3c2613f bellard
1029 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1030 67e999be bellard
void pcnet_h_reset(void *opaque);
1031 d537cf6c pbrook
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque, qemu_irq irq);
1032 67e999be bellard
1033 548df2ac ths
/* vmmouse.c */
1034 548df2ac ths
void *vmmouse_init(void *m);
1035 e3c2613f bellard
1036 80cabfad bellard
/* pckbd.c */
1037 80cabfad bellard
1038 b92bb99b ths
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1039 b92bb99b ths
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift);
1040 80cabfad bellard
1041 80cabfad bellard
/* mc146818rtc.c */
1042 80cabfad bellard
1043 8a7ddc38 bellard
typedef struct RTCState RTCState;
1044 80cabfad bellard
1045 d537cf6c pbrook
RTCState *rtc_init(int base, qemu_irq irq);
1046 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1047 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1048 80cabfad bellard
1049 80cabfad bellard
/* serial.c */
1050 80cabfad bellard
1051 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1052 d537cf6c pbrook
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1053 d537cf6c pbrook
SerialState *serial_mm_init (target_ulong base, int it_shift,
1054 d537cf6c pbrook
                             qemu_irq irq, CharDriverState *chr,
1055 a4bc3afc ths
                             int ioregister);
1056 a4bc3afc ths
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1057 a4bc3afc ths
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1058 a4bc3afc ths
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1059 a4bc3afc ths
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1060 a4bc3afc ths
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1061 a4bc3afc ths
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1062 80cabfad bellard
1063 6508fe59 bellard
/* parallel.c */
1064 6508fe59 bellard
1065 6508fe59 bellard
typedef struct ParallelState ParallelState;
1066 d537cf6c pbrook
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1067 6508fe59 bellard
1068 80cabfad bellard
/* i8259.c */
1069 80cabfad bellard
1070 3de388f6 bellard
typedef struct PicState2 PicState2;
1071 3de388f6 bellard
extern PicState2 *isa_pic;
1072 80cabfad bellard
void pic_set_irq(int irq, int level);
1073 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1074 d537cf6c pbrook
qemu_irq *i8259_init(qemu_irq parent_irq);
1075 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1076 d592d303 bellard
                          void *alt_irq_opaque);
1077 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1078 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1079 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1080 c20709aa bellard
void pic_info(void);
1081 4a0fb71e bellard
void irq_info(void);
1082 80cabfad bellard
1083 c27004ec bellard
/* APIC */
1084 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1085 d592d303 bellard
1086 c27004ec bellard
int apic_init(CPUState *env);
1087 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1088 d592d303 bellard
IOAPICState *ioapic_init(void);
1089 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1090 c27004ec bellard
1091 80cabfad bellard
/* i8254.c */
1092 80cabfad bellard
1093 80cabfad bellard
#define PIT_FREQ 1193182
1094 80cabfad bellard
1095 ec844b96 bellard
typedef struct PITState PITState;
1096 ec844b96 bellard
1097 d537cf6c pbrook
PITState *pit_init(int base, qemu_irq irq);
1098 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1099 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1100 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1101 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1102 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1103 80cabfad bellard
1104 fd06c375 bellard
/* pcspk.c */
1105 fd06c375 bellard
void pcspk_init(PITState *);
1106 d537cf6c pbrook
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1107 fd06c375 bellard
1108 3fffc223 ths
#include "hw/smbus.h"
1109 3fffc223 ths
1110 6515b203 bellard
/* acpi.c */
1111 6515b203 bellard
extern int acpi_enabled;
1112 502a5395 pbrook
void piix4_pm_init(PCIBus *bus, int devfn);
1113 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1114 6515b203 bellard
void acpi_bios_init(void);
1115 6515b203 bellard
1116 3fffc223 ths
/* smbus_eeprom.c */
1117 3fffc223 ths
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1118 3fffc223 ths
1119 80cabfad bellard
/* pc.c */
1120 54fa5af5 bellard
extern QEMUMachine pc_machine;
1121 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1122 52ca8d6a bellard
extern int fd_bootchk;
1123 80cabfad bellard
1124 6a00d601 bellard
void ioport_set_a20(int enable);
1125 6a00d601 bellard
int ioport_get_a20(void);
1126 6a00d601 bellard
1127 26aa7d72 bellard
/* ppc.c */
1128 54fa5af5 bellard
extern QEMUMachine prep_machine;
1129 54fa5af5 bellard
extern QEMUMachine core99_machine;
1130 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1131 54fa5af5 bellard
1132 6af0bf9c bellard
/* mips_r4k.c */
1133 6af0bf9c bellard
extern QEMUMachine mips_machine;
1134 6af0bf9c bellard
1135 5856de80 ths
/* mips_malta.c */
1136 5856de80 ths
extern QEMUMachine mips_malta_machine;
1137 5856de80 ths
1138 4de9b249 ths
/* mips_int */
1139 d537cf6c pbrook
extern void cpu_mips_irq_init_cpu(CPUState *env);
1140 4de9b249 ths
1141 e16fe40c ths
/* mips_timer.c */
1142 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1143 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1144 e16fe40c ths
1145 27c7ca7e bellard
/* shix.c */
1146 27c7ca7e bellard
extern QEMUMachine shix_machine;
1147 27c7ca7e bellard
1148 8cc43fef bellard
#ifdef TARGET_PPC
1149 47103572 j_mayer
/* PowerPC hardware exceptions management helpers */
1150 8cc43fef bellard
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1151 2e719ba3 j_mayer
/* Embedded PowerPC DCR management */
1152 2e719ba3 j_mayer
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1153 2e719ba3 j_mayer
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1154 2e719ba3 j_mayer
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1155 2e719ba3 j_mayer
                  int (*dcr_write_error)(int dcrn));
1156 2e719ba3 j_mayer
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1157 2e719ba3 j_mayer
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1158 8cc43fef bellard
#endif
1159 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1160 77d4bc34 bellard
1161 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1162 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1163 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1164 26aa7d72 bellard
1165 e95c8d51 bellard
/* sun4m.c */
1166 e0353fe2 blueswir1
extern QEMUMachine ss5_machine, ss10_machine;
1167 e95c8d51 bellard
1168 e95c8d51 bellard
/* iommu.c */
1169 e80cfcfc bellard
void *iommu_init(uint32_t addr);
1170 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1171 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1172 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1173 67e999be bellard
                                           target_phys_addr_t addr,
1174 67e999be bellard
                                           uint8_t *buf, int len)
1175 67e999be bellard
{
1176 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1177 67e999be bellard
}
1178 e95c8d51 bellard
1179 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1180 67e999be bellard
                                            target_phys_addr_t addr,
1181 67e999be bellard
                                            uint8_t *buf, int len)
1182 67e999be bellard
{
1183 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1184 67e999be bellard
}
1185 e95c8d51 bellard
1186 e95c8d51 bellard
/* tcx.c */
1187 95219897 pbrook
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1188 6f7e9aec bellard
               unsigned long vram_offset, int vram_size, int width, int height);
1189 e80cfcfc bellard
1190 e80cfcfc bellard
/* slavio_intctl.c */
1191 52cc07d0 blueswir1
void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1192 e0353fe2 blueswir1
void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
1193 d537cf6c pbrook
                         const uint32_t *intbit_to_level,
1194 d537cf6c pbrook
                         qemu_irq **irq);
1195 ba3c64fb bellard
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1196 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1197 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1198 e95c8d51 bellard
1199 5fe141fd bellard
/* loader.c */
1200 5fe141fd bellard
int get_image_size(const char *filename);
1201 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1202 74287114 ths
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1203 74287114 ths
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1204 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1205 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1206 e80cfcfc bellard
1207 e80cfcfc bellard
/* slavio_timer.c */
1208 52cc07d0 blueswir1
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
1209 52cc07d0 blueswir1
                       void *intctl);
1210 8d5f07fa bellard
1211 e80cfcfc bellard
/* slavio_serial.c */
1212 d537cf6c pbrook
SerialState *slavio_serial_init(int base, qemu_irq irq, CharDriverState *chr1,
1213 d537cf6c pbrook
                                CharDriverState *chr2);
1214 d537cf6c pbrook
void slavio_serial_ms_kbd_init(int base, qemu_irq);
1215 e95c8d51 bellard
1216 3475187d bellard
/* slavio_misc.c */
1217 d537cf6c pbrook
void *slavio_misc_init(uint32_t base, qemu_irq irq);
1218 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1219 3475187d bellard
1220 6f7e9aec bellard
/* esp.c */
1221 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1222 67e999be bellard
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1223 67e999be bellard
void esp_reset(void *opaque);
1224 67e999be bellard
1225 67e999be bellard
/* sparc32_dma.c */
1226 d537cf6c pbrook
void *sparc32_dma_init(uint32_t daddr, qemu_irq espirq, qemu_irq leirq,
1227 d537cf6c pbrook
                       void *iommu);
1228 67e999be bellard
void ledma_set_irq(void *opaque, int isr);
1229 9b94dc32 bellard
void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
1230 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1231 9b94dc32 bellard
void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
1232 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1233 67e999be bellard
void espdma_raise_irq(void *opaque);
1234 67e999be bellard
void espdma_clear_irq(void *opaque);
1235 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1236 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1237 67e999be bellard
void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1238 67e999be bellard
                                void *lance_opaque);
1239 6f7e9aec bellard
1240 b8174937 bellard
/* cs4231.c */
1241 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1242 b8174937 bellard
1243 3475187d bellard
/* sun4u.c */
1244 3475187d bellard
extern QEMUMachine sun4u_machine;
1245 3475187d bellard
1246 64201201 bellard
/* NVRAM helpers */
1247 64201201 bellard
#include "hw/m48t59.h"
1248 64201201 bellard
1249 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1250 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1251 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1252 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1253 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1254 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1255 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1256 64201201 bellard
                       const unsigned char *str, uint32_t max);
1257 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1258 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1259 64201201 bellard
                    uint32_t start, uint32_t count);
1260 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1261 64201201 bellard
                          const unsigned char *arch,
1262 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1263 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1264 28b9b5af bellard
                          const char *cmdline,
1265 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1266 28b9b5af bellard
                          uint32_t NVRAM_image,
1267 28b9b5af bellard
                          int width, int height, int depth);
1268 64201201 bellard
1269 63066f4f bellard
/* adb.c */
1270 63066f4f bellard
1271 63066f4f bellard
#define MAX_ADB_DEVICES 16
1272 63066f4f bellard
1273 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1274 63066f4f bellard
1275 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1276 63066f4f bellard
1277 e2733d20 bellard
/* buf = NULL means polling */
1278 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1279 e2733d20 bellard
                              const uint8_t *buf, int len);
1280 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1281 12c28fed bellard
1282 63066f4f bellard
struct ADBDevice {
1283 63066f4f bellard
    struct ADBBusState *bus;
1284 63066f4f bellard
    int devaddr;
1285 63066f4f bellard
    int handler;
1286 e2733d20 bellard
    ADBDeviceRequest *devreq;
1287 12c28fed bellard
    ADBDeviceReset *devreset;
1288 63066f4f bellard
    void *opaque;
1289 63066f4f bellard
};
1290 63066f4f bellard
1291 63066f4f bellard
typedef struct ADBBusState {
1292 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1293 63066f4f bellard
    int nb_devices;
1294 e2733d20 bellard
    int poll_index;
1295 63066f4f bellard
} ADBBusState;
1296 63066f4f bellard
1297 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1298 e2733d20 bellard
                const uint8_t *buf, int len);
1299 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1300 63066f4f bellard
1301 63066f4f bellard
ADBDevice *adb_register_device(ADBBusState *s, int devaddr, 
1302 e2733d20 bellard
                               ADBDeviceRequest *devreq, 
1303 12c28fed bellard
                               ADBDeviceReset *devreset, 
1304 63066f4f bellard
                               void *opaque);
1305 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1306 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1307 63066f4f bellard
1308 63066f4f bellard
/* cuda.c */
1309 63066f4f bellard
1310 63066f4f bellard
extern ADBBusState adb_bus;
1311 d537cf6c pbrook
int cuda_init(qemu_irq irq);
1312 63066f4f bellard
1313 bb36d470 bellard
#include "hw/usb.h"
1314 bb36d470 bellard
1315 a594cfbf bellard
/* usb ports of the VM */
1316 a594cfbf bellard
1317 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1318 0d92ed30 pbrook
                            usb_attachfn attach);
1319 a594cfbf bellard
1320 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1321 a594cfbf bellard
1322 a594cfbf bellard
void do_usb_add(const char *devname);
1323 a594cfbf bellard
void do_usb_del(const char *devname);
1324 a594cfbf bellard
void usb_info(void);
1325 a594cfbf bellard
1326 2e5d83bb pbrook
/* scsi-disk.c */
1327 4d611c9a pbrook
enum scsi_reason {
1328 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1329 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1330 4d611c9a pbrook
};
1331 4d611c9a pbrook
1332 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1333 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1334 a917d384 pbrook
                                  uint32_t arg);
1335 2e5d83bb pbrook
1336 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1337 a917d384 pbrook
                           int tcq,
1338 2e5d83bb pbrook
                           scsi_completionfn completion,
1339 2e5d83bb pbrook
                           void *opaque);
1340 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1341 2e5d83bb pbrook
1342 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1343 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1344 4d611c9a pbrook
   layer the completion routine may be called directly by
1345 4d611c9a pbrook
   scsi_{read,write}_data.  */
1346 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1347 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1348 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1349 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1350 2e5d83bb pbrook
1351 7d8406be pbrook
/* lsi53c895a.c */
1352 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1353 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1354 7d8406be pbrook
1355 b5ff1b31 bellard
/* integratorcp.c */
1356 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1357 b5ff1b31 bellard
1358 cdbdb648 pbrook
/* versatilepb.c */
1359 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1360 16406950 pbrook
extern QEMUMachine versatileab_machine;
1361 cdbdb648 pbrook
1362 e69954b9 pbrook
/* realview.c */
1363 e69954b9 pbrook
extern QEMUMachine realview_machine;
1364 e69954b9 pbrook
1365 daa57963 bellard
/* ps2.c */
1366 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1367 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1368 daa57963 bellard
void ps2_write_mouse(void *, int val);
1369 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1370 daa57963 bellard
uint32_t ps2_read_data(void *);
1371 daa57963 bellard
void ps2_queue(void *, int b);
1372 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1373 548df2ac ths
void ps2_mouse_fake_event(void *opaque);
1374 daa57963 bellard
1375 80337b66 bellard
/* smc91c111.c */
1376 d537cf6c pbrook
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1377 80337b66 bellard
1378 bdd5003a pbrook
/* pl110.c */
1379 d537cf6c pbrook
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1380 bdd5003a pbrook
1381 cdbdb648 pbrook
/* pl011.c */
1382 d537cf6c pbrook
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1383 cdbdb648 pbrook
1384 cdbdb648 pbrook
/* pl050.c */
1385 d537cf6c pbrook
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1386 cdbdb648 pbrook
1387 cdbdb648 pbrook
/* pl080.c */
1388 d537cf6c pbrook
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1389 cdbdb648 pbrook
1390 a1bb27b1 pbrook
/* pl181.c */
1391 a1bb27b1 pbrook
void pl181_init(uint32_t base, BlockDriverState *bd,
1392 d537cf6c pbrook
                qemu_irq irq0, qemu_irq irq1);
1393 a1bb27b1 pbrook
1394 cdbdb648 pbrook
/* pl190.c */
1395 d537cf6c pbrook
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1396 cdbdb648 pbrook
1397 cdbdb648 pbrook
/* arm-timer.c */
1398 d537cf6c pbrook
void sp804_init(uint32_t base, qemu_irq irq);
1399 d537cf6c pbrook
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1400 cdbdb648 pbrook
1401 e69954b9 pbrook
/* arm_sysctl.c */
1402 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1403 e69954b9 pbrook
1404 e69954b9 pbrook
/* arm_gic.c */
1405 d537cf6c pbrook
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1406 e69954b9 pbrook
1407 16406950 pbrook
/* arm_boot.c */
1408 16406950 pbrook
1409 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1410 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1411 16406950 pbrook
                     int board_id);
1412 16406950 pbrook
1413 27c7ca7e bellard
/* sh7750.c */
1414 27c7ca7e bellard
struct SH7750State;
1415 27c7ca7e bellard
1416 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1417 27c7ca7e bellard
1418 27c7ca7e bellard
typedef struct {
1419 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1420 27c7ca7e bellard
    uint16_t portamask_trigger;
1421 27c7ca7e bellard
    uint16_t portbmask_trigger;
1422 27c7ca7e bellard
    /* Return 0 if no action was taken */
1423 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1424 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1425 27c7ca7e bellard
                           uint16_t * periph_portdira,
1426 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1427 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1428 27c7ca7e bellard
} sh7750_io_device;
1429 27c7ca7e bellard
1430 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1431 27c7ca7e bellard
                              sh7750_io_device * device);
1432 27c7ca7e bellard
/* tc58128.c */
1433 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1434 27c7ca7e bellard
1435 29133e9a bellard
/* NOR flash devices */
1436 29133e9a bellard
typedef struct pflash_t pflash_t;
1437 29133e9a bellard
1438 29133e9a bellard
pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1439 29133e9a bellard
                           BlockDriverState *bs,
1440 29133e9a bellard
                           target_ulong sector_len, int nb_blocs, int width,
1441 29133e9a bellard
                           uint16_t id0, uint16_t id1, 
1442 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1443 29133e9a bellard
1444 4046d913 pbrook
#include "gdbstub.h"
1445 4046d913 pbrook
1446 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1447 ea2384d3 bellard
1448 c4b1fcc0 bellard
/* monitor.c */
1449 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1450 ea2384d3 bellard
void term_puts(const char *str);
1451 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1452 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1453 fef30743 ths
void term_print_filename(const char *filename);
1454 c4b1fcc0 bellard
void term_flush(void);
1455 c4b1fcc0 bellard
void term_print_help(void);
1456 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1457 ea2384d3 bellard
                      char *buf, int buf_size);
1458 ea2384d3 bellard
1459 ea2384d3 bellard
/* readline.c */
1460 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1461 ea2384d3 bellard
1462 ea2384d3 bellard
extern int completion_index;
1463 ea2384d3 bellard
void add_completion(const char *str);
1464 ea2384d3 bellard
void readline_handle_byte(int ch);
1465 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1466 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1467 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1468 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1469 c4b1fcc0 bellard
1470 5e6ad6f9 bellard
void kqemu_record_dump(void);
1471 5e6ad6f9 bellard
1472 fc01f7e7 bellard
#endif /* VL_H */