Revision b946a153 hw/mipsnet.c
| b/hw/mipsnet.c | ||
|---|---|---|
| 33 | 33 |
uint32_t intctl; |
| 34 | 34 |
uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; |
| 35 | 35 |
uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; |
| 36 |
int io_base; |
|
| 36 | 37 |
qemu_irq irq; |
| 37 | 38 |
VLANClientState *vc; |
| 38 | 39 |
} MIPSnetState; |
| ... | ... | |
| 231 | 232 |
return 0; |
| 232 | 233 |
} |
| 233 | 234 |
|
| 235 |
static void mipsnet_cleanup(VLANClientState *vc) |
|
| 236 |
{
|
|
| 237 |
MIPSnetState *s = vc->opaque; |
|
| 238 |
|
|
| 239 |
unregister_savevm("mipsnet", s);
|
|
| 240 |
|
|
| 241 |
isa_unassign_ioport(s->io_base, 36); |
|
| 242 |
|
|
| 243 |
qemu_free(s); |
|
| 244 |
} |
|
| 245 |
|
|
| 234 | 246 |
void mipsnet_init (int base, qemu_irq irq, NICInfo *nd) |
| 235 | 247 |
{
|
| 236 | 248 |
MIPSnetState *s; |
| ... | ... | |
| 246 | 258 |
register_ioport_write(base, 36, 4, mipsnet_ioport_write, s); |
| 247 | 259 |
register_ioport_read(base, 36, 4, mipsnet_ioport_read, s); |
| 248 | 260 |
|
| 261 |
s->io_base = base; |
|
| 249 | 262 |
s->irq = irq; |
| 250 | 263 |
if (nd && nd->vlan) {
|
| 251 | 264 |
s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
| 252 |
mipsnet_receive, mipsnet_can_receive, s); |
|
| 265 |
mipsnet_receive, mipsnet_can_receive, |
|
| 266 |
mipsnet_cleanup, s); |
|
| 253 | 267 |
} else {
|
| 254 | 268 |
s->vc = NULL; |
| 255 | 269 |
} |
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