Archipelago » qemu

    /* XXX: are the three pins inverted inside the chip between the

     * tsc and the cpu (N4111)?  */

    qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];

    qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];

static void n8x0_dss_setup(struct n800_s *s)

{

    s->blizzard.block = s1d13745_write_block;

    s->blizzard.write = s1d13745_write;

    s->blizzard.read = s1d13745_read;

    /* Using the NOR interface */

    omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,

    omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,

    s->usb = tusb;

    omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);

        "headphone", N8X0_HEADPHONE_GPIO,

        OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,

    },

}, n810_gpiosw_info[] = {

    {

        "gps_reset", N810_GPS_RESET_GPIO,

        "slide", N810_SLIDE_GPIO,

        OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,

    },

};

static struct omap_partition_info_s {

    { 0x00280000, 0x00200000, 0x3, "initfs" },

    { 0x00480000, 0x0fb80000, 0x3, "rootfs" },

}, n810_part_info[] = {

    { 0x00000000, 0x00020000, 0x3, "bootloader" },

    { 0x00020000, 0x00060000, 0x0, "config" },

    { 0x002a0000, 0x00400000, 0x0, "initfs" },

    { 0x006a0000, 0x0f960000, 0x0, "rootfs" },

};

static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int offset = addr;

    int bank_no, line_no;

    if ((offset & 0xf80) == 0x80) {

        bank_no = (offset & 0x60) >> 5;

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int offset = addr;

    int bank_no, line_no;

    if ((offset & 0xf80) == 0x80) {

        bank_no = (offset & 0x60) >> 5;

                    omap_findclk(s, "uart2_ck"),

                    omap_findclk(s, "uart2_ck"),

                    s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],

    s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],

                    omap_findclk(s, "uart3_ck"),

                    omap_findclk(s, "uart3_ck"),

                    s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],

    omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));

    omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));

    s->modules = modules;

    for (i = 0; i < modules; i ++)

        omap_gpio_module_init(s->module + i, ta, region[i],

    omap_gpif_reset(s);

    if (s->codec.in_voice) {

        AUD_set_active_in(s->codec.in_voice, 0);

        AUD_close_in(&s->codec.card, s->codec.in_voice);

    }

    if (s->codec.out_voice) {

        omap_eac_out_empty(s);

        AUD_set_active_out(s->codec.out_voice, 0);

        AUD_close_out(&s->codec.card, s->codec.out_voice);

        s->codec.txavail = 0;

    }

    /* Discard what couldn't be written */

struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)

{

    int i, iomemtype;

    for (i = 0; i < bus->ta_num; i ++)

        if (omap_l4_agent_info[i].ta == cs) {

                    omap_findclk(s, "uart2_iclk"),

                    s->drq[OMAP24XX_DMA_UART2_TX],

                    s->drq[OMAP24XX_DMA_UART2_RX],

    s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),

                    s->irq[0][OMAP_INT_24XX_UART3_IRQ],

                    omap_findclk(s, "uart3_fclk"),

                    omap_findclk(s, "uart3_iclk"),

                    s->drq[OMAP24XX_DMA_UART3_TX],

                    s->drq[OMAP24XX_DMA_UART3_RX],

    s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),

                    s->irq[0][OMAP_INT_24XX_GPTIMER1],

    omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,

                    s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),

                    serial_hds[0] && serial_hds[1] && serial_hds[2] ?

    s->eac = omap_eac_init(omap_l4ta(s->l4, 32),

                    s->irq[0][OMAP_INT_24XX_EAC_IRQ],

    &dss_l4_iclk,

    &omapctrl_clk,

};

void omap_clk_adduser(struct clk *clk, qemu_irq user)

        omap_clk_update(clk);

        omap_clk_rate_update(clk);

    } else

}

void omap_clk_onoff(struct clk *clk, int on)

#include "omap_lcd_template.h"

static draw_line_func draw_line_table2[33] = {

    [8]		= draw_line2_8,

    [15]	= draw_line2_15,

    [16]	= draw_line2_16,

    [32]	= draw_line2_32,

}, draw_line_table4[33] = {

    [8]		= draw_line4_8,

    [15]	= draw_line4_15,

    [16]	= draw_line4_16,

    [32]	= draw_line4_32,

}, draw_line_table8[33] = {

    [8]		= draw_line8_8,

    [15]	= draw_line8_15,

    [16]	= draw_line8_16,

    [32]	= draw_line8_32,

}, draw_line_table12[33] = {

    [8]		= draw_line12_8,

    [15]	= draw_line12_15,

    [16]	= draw_line12_16,

    [32]	= draw_line12_32,

}, draw_line_table16[33] = {

    [8]		= draw_line16_8,

    [15]	= draw_line16_15,

    [16]	= draw_line16_16,

    s->card = sd_init(bd, 0);

    s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0];

    return s;

}

    case 0x65:	/* OTP Access */

        s->intstatus |= ONEN_INT;

        s->current = s->otp;

        s->secs_cur = 1 << (BLOCK_SHIFT - 9);

        s->addr[ONEN_BUF_BLOCK] = 0;

    s->shift = regshift;

    s->intr = irq;

    s->id = id;

    s->blocks = size >> BLOCK_SHIFT;

    s->secs = size >> 9;

                target_phys_addr_t addr, int *miny, int *maxy)

{

    int src_width, dest_width;

    if (s->dest_width)

        fn = s->line_fn[s->transp][s->bpp];

    if (!fn)

               target_phys_addr_t addr, int *miny, int *maxy)

{

    int src_width, dest_width;

    if (s->dest_width)

        fn = s->line_fn[s->transp][s->bpp];

    if (!fn)

        return -ENOENT;

    s->card->detach(s->card->state);

    s->slot.attached = 0;

/* Overlay planes disabled, no transparency */

static drawfn glue(pxa2xx_draw_fn_, BITS)[16] =

{

    [pxa_lcdc_2bpp]   = glue(pxa2xx_draw_line2_, BITS),

    [pxa_lcdc_4bpp]   = glue(pxa2xx_draw_line4_, BITS),

    [pxa_lcdc_8bpp]   = glue(pxa2xx_draw_line8_, BITS),

/* Overlay planes enabled, transparency used */

static drawfn glue(glue(pxa2xx_draw_fn_, BITS), t)[16] =

{

    [pxa_lcdc_4bpp]   = glue(pxa2xx_draw_line4_, BITS),

    [pxa_lcdc_8bpp]   = glue(pxa2xx_draw_line8_, BITS),

    [pxa_lcdc_16bpp]  = glue(pxa2xx_draw_line16t_, BITS),

{

    pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);

    s->freq = PXA25X_FREQ;

}

void pxa27x_timer_init(target_phys_addr_t base,

	REGNAME(SH7750_BCR3_A7)

	REGNAME(SH7750_BCR4_A7)

	REGNAME(SH7750_SDMR2_A7)

};

const char *regname(uint32_t addr)

    /* bridge to serial emulation module */

    if (chr)

	serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,

		       115200, chr, 1);

    /* create qemu graphic console */

        s->codec.out.size = 0;

        AUD_set_active_out(s->dac_voice[0], 0);

        AUD_close_out(&s->card, s->dac_voice[0]);

    }

    s->codec.cts = 0;

#include <stdio.h>

CPUARMState* user_registers;

/* Reset the FPA11 chip.  Called to initialize and reset the emulator. */

	memory_content *next = current->next;

	free (current);

	env->movcal_backup = current = next;

	    env->movcal_backup_tail = &(env->movcal_backup);

    } 

}

	    memory_content *next = (*current)->next;

	    stl(a, (*current)->value);

	    {

		env->movcal_backup_tail = current;

	    }