Revision ba3c64fb hw/slavio_intctl.c
| b/hw/slavio_intctl.c | ||
|---|---|---|
| 53 | 53 |
#ifdef DEBUG_IRQ_COUNT |
| 54 | 54 |
uint64_t irq_count[32]; |
| 55 | 55 |
#endif |
| 56 |
CPUState *cpu_envs[MAX_CPUS]; |
|
| 56 | 57 |
} SLAVIO_INTCTLState; |
| 57 | 58 |
|
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#define INTCTL_MAXADDR 0xf |
| ... | ... | |
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case 2: // set softint |
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val &= 0xfffe0000; |
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s->intreg_pending[cpu] |= val; |
| 100 |
slavio_check_interrupts(s); |
|
| 99 | 101 |
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
| 100 | 102 |
break; |
| 101 | 103 |
default: |
| ... | ... | |
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CPUState *env; |
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SLAVIO_INTCTLState *s = opaque; |
| 218 | 220 |
uint32_t pending = s->intregm_pending; |
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unsigned int i, max = 0; |
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unsigned int i, j, max = 0;
|
|
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|
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pending &= ~s->intregm_disabled; |
| 222 | 224 |
|
| ... | ... | |
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max = intbit_to_level[i]; |
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} |
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} |
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env = first_cpu; |
|
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered pil %d\n", max);
|
|
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env = s->cpu_envs[s->target_cpu]; |
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if (!env) {
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DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
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} |
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else {
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if (env->halted) |
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env->halted = 0; |
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
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|
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#ifdef DEBUG_IRQ_COUNT |
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s->irq_count[max]++;
|
|
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s->irq_count[max]++;
|
|
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#endif |
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env->interrupt_index = TT_EXTINT | max; |
|
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
|
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env->interrupt_index = TT_EXTINT | max; |
|
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
|
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} |
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else |
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DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
|
|
| 238 | 249 |
} |
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else |
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DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
|
|
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} |
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else |
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DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
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|
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for (i = 0; i < MAX_CPUS; i++) {
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max = 0; |
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env = s->cpu_envs[i]; |
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if (!env) |
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continue; |
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for (j = 17; j < 32; j++) {
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if (s->intreg_pending[i] & (1 << j)) {
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if (max < j - 16) |
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max = j - 16; |
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} |
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} |
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if (max > 0) {
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if (env->halted) |
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env->halted = 0; |
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
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#ifdef DEBUG_IRQ_COUNT |
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s->irq_count[max]++; |
|
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#endif |
|
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env->interrupt_index = TT_EXTINT | max; |
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
|
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} |
|
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} |
|
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} |
|
| 244 | 278 |
} |
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|
| 246 | 280 |
/* |
| ... | ... | |
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{
|
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SLAVIO_INTCTLState *s = opaque; |
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|
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DPRINTF("Set irq %d level %d\n", irq, level);
|
|
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DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
|
|
| 255 | 289 |
if (irq < 32) {
|
| 256 | 290 |
uint32_t mask = 1 << irq; |
| 257 | 291 |
uint32_t pil = intbit_to_level[irq]; |
| ... | ... | |
| 269 | 303 |
slavio_check_interrupts(s); |
| 270 | 304 |
} |
| 271 | 305 |
|
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void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu) |
|
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{
|
|
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SLAVIO_INTCTLState *s = opaque; |
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|
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DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
|
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if (cpu == (unsigned int)-1) {
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slavio_pic_set_irq(opaque, irq, level); |
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return; |
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} |
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if (irq < 32) {
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uint32_t pil = intbit_to_level[irq]; |
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if (pil > 0) {
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if (level) {
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s->intreg_pending[cpu] |= 1 << pil; |
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} |
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else {
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s->intreg_pending[cpu] &= ~(1 << pil); |
|
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} |
|
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} |
|
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} |
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slavio_check_interrupts(s); |
|
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} |
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|
|
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static void slavio_intctl_save(QEMUFile *f, void *opaque) |
| 273 | 330 |
{
|
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SLAVIO_INTCTLState *s = opaque; |
| ... | ... | |
| 312 | 369 |
s->target_cpu = 0; |
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} |
| 314 | 371 |
|
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void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env) |
|
| 373 |
{
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SLAVIO_INTCTLState *s = opaque; |
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s->cpu_envs[cpu] = env; |
|
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} |
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|
|
| 315 | 378 |
void *slavio_intctl_init(uint32_t addr, uint32_t addrg) |
| 316 | 379 |
{
|
| 317 | 380 |
int slavio_intctl_io_memory, slavio_intctlm_io_memory, i; |
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