Revision ba6a9d8c target-sparc/cpu.h

b/target-sparc/cpu.h
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#endif
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/* Fcc */


  		





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#define FSR_RD1        (1<<31)


  		





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#define FSR_RD0        (1<<30)


  		





  
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#define FSR_RD1        (1ULL << 31)


  		





  
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#define FSR_RD0        (1ULL << 30)


  		





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#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)


  		





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#define FSR_RD_NEAREST 0


  		





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#define FSR_RD_ZERO    FSR_RD0


  		





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#define FSR_RD_POS     FSR_RD1


  		





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#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)


  		





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#define FSR_NVM   (1<<27)


  		





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#define FSR_OFM   (1<<26)


  		





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#define FSR_UFM   (1<<25)


  		





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#define FSR_DZM   (1<<24)


  		





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#define FSR_NXM   (1<<23)


  		





  
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#define FSR_NVM   (1ULL << 27)


  		





  
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#define FSR_OFM   (1ULL << 26)


  		





  
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#define FSR_UFM   (1ULL << 25)


  		





  
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#define FSR_DZM   (1ULL << 24)


  		





  
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#define FSR_NXM   (1ULL << 23)


  		





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#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)


  		





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#define FSR_NVA   (1<<9)


  		





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#define FSR_OFA   (1<<8)


  		





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#define FSR_UFA   (1<<7)


  		





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#define FSR_DZA   (1<<6)


  		





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#define FSR_NXA   (1<<5)


  		





  
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#define FSR_NVA   (1ULL << 9)


  		





  
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#define FSR_OFA   (1ULL << 8)


  		





  
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#define FSR_UFA   (1ULL << 7)


  		





  
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#define FSR_DZA   (1ULL << 6)


  		





  
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#define FSR_NXA   (1ULL << 5)


  		





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#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)


  		





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#define FSR_NVC   (1<<4)


  		





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#define FSR_OFC   (1<<3)


  		





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#define FSR_UFC   (1<<2)


  		





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#define FSR_DZC   (1<<1)


  		





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#define FSR_NXC   (1<<0)


  		





  
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#define FSR_NVC   (1ULL << 4)


  		





  
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#define FSR_OFC   (1ULL << 3)


  		





  
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#define FSR_UFC   (1ULL << 2)


  		





  
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#define FSR_DZC   (1ULL << 1)


  		





  
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#define FSR_NXC   (1ULL << 0)


  		





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#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)


  		





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#define FSR_FTT2   (1<<16)


  		





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#define FSR_FTT1   (1<<15)


  		





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#define FSR_FTT0   (1<<14)


  		





  
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#define FSR_FTT2   (1ULL << 16)


  		





  
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#define FSR_FTT1   (1ULL << 15)


  		





  
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#define FSR_FTT0   (1ULL << 14)


  		





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#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)


  		





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#define FSR_FTT_IEEE_EXCP (1 << 14)


  		





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#define FSR_FTT_UNIMPFPOP (3 << 14)


  		





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#define FSR_FTT_SEQ_ERROR (4 << 14)


  		





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#define FSR_FTT_INVAL_FPR (6 << 14)


  		





  
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#define FSR_FTT_IEEE_EXCP (1ULL << 14)


  		





  
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#define FSR_FTT_UNIMPFPOP (3ULL << 14)


  		





  
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#define FSR_FTT_SEQ_ERROR (4ULL << 14)


  		





  
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#define FSR_FTT_INVAL_FPR (6ULL << 14)


  		





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#define FSR_FCC1_SHIFT 11


  		





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#define FSR_FCC1  (1 << FSR_FCC1_SHIFT)


  		





  
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#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)


  		





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#define FSR_FCC0_SHIFT 10


  		





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#define FSR_FCC0  (1 << FSR_FCC0_SHIFT)


  		





  
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#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)


  		





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/* MMU */


  		





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#define MMU_E     (1<<0)


  		












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