Archipelago » qemu

/*

 *  PowerPC CPU initialization for qemu.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

/* A lot of PowerPC definition have been included here.

 * Most of them are not usable for now but have been kept

 * inside "#if defined(TODO) ... #endif" statements to make tests easier.

 */

#include "dis-asm.h"

#include "gdbstub.h"

//#define PPC_DUMP_CPU

//#define PPC_DEBUG_SPR

//#define PPC_DUMP_SPR_ACCESSES

#if defined(CONFIG_USER_ONLY)

#define TODO_USER_ONLY 1

#endif

struct ppc_def_t {

    const char *name;

    uint32_t pvr;

    uint32_t svr;

    uint64_t insns_flags;

    uint64_t msr_mask;

    powerpc_mmu_t   mmu_model;

    powerpc_excp_t  excp_model;

    powerpc_input_t bus_model;

    uint32_t flags;

    int bfd_mach;

    void (*init_proc)(CPUPPCState *env);

    int  (*check_pow)(CPUPPCState *env);

};

/* For user-mode emulation, we don't emulate any IRQ controller */

#if defined(CONFIG_USER_ONLY)

#define PPC_IRQ_INIT_FN(name)                                                 \

static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \

{                                                                             \

}

#else

#define PPC_IRQ_INIT_FN(name)                                                 \

void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);

#endif

PPC_IRQ_INIT_FN(40x);

PPC_IRQ_INIT_FN(6xx);

PPC_IRQ_INIT_FN(970);

PPC_IRQ_INIT_FN(e500);

/* Generic callbacks:

 * do nothing but store/retrieve spr value

 */

static void spr_read_generic (void *opaque, int gprn, int sprn)

{

    gen_load_spr(cpu_gpr[gprn], sprn);

#ifdef PPC_DUMP_SPR_ACCESSES

    {

        TCGv t0 = tcg_const_i32(sprn);

        gen_helper_load_dump_spr(t0);

        tcg_temp_free_i32(t0);

    }

#endif

}

static void spr_write_generic (void *opaque, int sprn, int gprn)

{

    gen_store_spr(sprn, cpu_gpr[gprn]);

#ifdef PPC_DUMP_SPR_ACCESSES

    {

        TCGv t0 = tcg_const_i32(sprn);

        gen_helper_store_dump_spr(t0);

        tcg_temp_free_i32(t0);

    }

#endif

}

#if !defined(CONFIG_USER_ONLY)

static void spr_write_clear (void *opaque, int sprn, int gprn)

{

    TCGv t0 = tcg_temp_new();

    TCGv t1 = tcg_temp_new();

    gen_load_spr(t0, sprn);

    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);

    tcg_gen_and_tl(t0, t0, t1);

    gen_store_spr(sprn, t0);

    tcg_temp_free(t0);

    tcg_temp_free(t1);

}

#endif

/* SPR common to all PowerPC */

/* XER */

static void spr_read_xer (void *opaque, int gprn, int sprn)

{

    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);

}

static void spr_write_xer (void *opaque, int sprn, int gprn)

{

    tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);

}

/* LR */

static void spr_read_lr (void *opaque, int gprn, int sprn)

{

    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);

}

static void spr_write_lr (void *opaque, int sprn, int gprn)

{

    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);

}

/* CTR */

static void spr_read_ctr (void *opaque, int gprn, int sprn)

{

    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);

}

static void spr_write_ctr (void *opaque, int sprn, int gprn)

{

    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);

}

/* User read access to SPR */

/* USPRx */

/* UMMCRx */

/* UPMCx */

/* USIA */

/* UDECR */

static void spr_read_ureg (void *opaque, int gprn, int sprn)

{

    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);

}

/* SPR common to all non-embedded PowerPC */

/* DECR */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_decr (void *opaque, int gprn, int sprn)

{

    if (use_icount) {

        gen_io_start();

    }

    gen_helper_load_decr(cpu_gpr[gprn]);

    if (use_icount) {

        gen_io_end();

        gen_stop_exception(opaque);

    }

}

static void spr_write_decr (void *opaque, int sprn, int gprn)

{

    if (use_icount) {

        gen_io_start();

    }

    gen_helper_store_decr(cpu_gpr[gprn]);

    if (use_icount) {

        gen_io_end();

        gen_stop_exception(opaque);

    }

}

#endif

/* SPR common to all non-embedded PowerPC, except 601 */

/* Time base */

static void spr_read_tbl (void *opaque, int gprn, int sprn)

{

    if (use_icount) {

        gen_io_start();

    }

    gen_helper_load_tbl(cpu_gpr[gprn]);

    if (use_icount) {

        gen_io_end();

        gen_stop_exception(opaque);

    }

}

static void spr_read_tbu (void *opaque, int gprn, int sprn)

{

    if (use_icount) {

        gen_io_start();

    }

    gen_helper_load_tbu(cpu_gpr[gprn]);

    if (use_icount) {

        gen_io_end();

        gen_stop_exception(opaque);

    }

}

__attribute__ (( unused ))

static void spr_read_atbl (void *opaque, int gprn, int sprn)

{

    gen_helper_load_atbl(cpu_gpr[gprn]);

}

__attribute__ (( unused ))

static void spr_read_atbu (void *opaque, int gprn, int sprn)

{

    gen_helper_load_atbu(cpu_gpr[gprn]);

}

#if !defined(CONFIG_USER_ONLY)

static void spr_write_tbl (void *opaque, int sprn, int gprn)

{

    if (use_icount) {

        gen_io_start();

    }

    gen_helper_store_tbl(cpu_gpr[gprn]);

    if (use_icount) {

        gen_io_end();

        gen_stop_exception(opaque);

    }

}

static void spr_write_tbu (void *opaque, int sprn, int gprn)

{

    if (use_icount) {

        gen_io_start();

    }

    gen_helper_store_tbu(cpu_gpr[gprn]);

    if (use_icount) {

        gen_io_end();

        gen_stop_exception(opaque);

    }

}

__attribute__ (( unused ))

static void spr_write_atbl (void *opaque, int sprn, int gprn)

{

    gen_helper_store_atbl(cpu_gpr[gprn]);

}

__attribute__ (( unused ))

static void spr_write_atbu (void *opaque, int sprn, int gprn)

{

    gen_helper_store_atbu(cpu_gpr[gprn]);

}

#endif

#if !defined(CONFIG_USER_ONLY)

/* IBAT0U...IBAT0U */

/* IBAT0L...IBAT7L */

static void spr_read_ibat (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));

}

static void spr_read_ibat_h (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));

}

static void spr_write_ibatu (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);

    gen_helper_store_ibatu(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);

    gen_helper_store_ibatu(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_ibatl (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);

    gen_helper_store_ibatl(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);

    gen_helper_store_ibatl(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

/* DBAT0U...DBAT7U */

/* DBAT0L...DBAT7L */

static void spr_read_dbat (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));

}

static void spr_read_dbat_h (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));

}

static void spr_write_dbatu (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);

    gen_helper_store_dbatu(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);

    gen_helper_store_dbatu(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_dbatl (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);

    gen_helper_store_dbatl(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);

    gen_helper_store_dbatl(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

/* SDR1 */

static void spr_read_sdr1 (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));

}

static void spr_write_sdr1 (void *opaque, int sprn, int gprn)

{

    gen_helper_store_sdr1(cpu_gpr[gprn]);

}

/* 64 bits PowerPC specific SPRs */

/* ASR */

#if defined(TARGET_PPC64)

static void spr_read_hior (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));

}

static void spr_write_hior (void *opaque, int sprn, int gprn)

{

    TCGv t0 = tcg_temp_new();

    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);

    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));

    tcg_temp_free(t0);

}

static void spr_read_asr (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));

}

static void spr_write_asr (void *opaque, int sprn, int gprn)

{

    gen_helper_store_asr(cpu_gpr[gprn]);

}

#endif

#endif

/* PowerPC 601 specific registers */

/* RTC */

static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)

{

    gen_helper_load_601_rtcl(cpu_gpr[gprn]);

}

static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)

{

    gen_helper_load_601_rtcu(cpu_gpr[gprn]);

}

#if !defined(CONFIG_USER_ONLY)

static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)

{

    gen_helper_store_601_rtcu(cpu_gpr[gprn]);

}

static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)

{

    gen_helper_store_601_rtcl(cpu_gpr[gprn]);

}

static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)

{

    DisasContext *ctx = opaque;

    gen_helper_store_hid0_601(cpu_gpr[gprn]);

    /* Must stop the translation as endianness may have changed */

    gen_stop_exception(ctx);

}

#endif

/* Unified bats */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_601_ubat (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));

}

static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);

    gen_helper_store_601_batl(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);

    gen_helper_store_601_batu(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

#endif

/* PowerPC 40x specific registers */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_40x_pit (void *opaque, int gprn, int sprn)

{

    gen_helper_load_40x_pit(cpu_gpr[gprn]);

}

static void spr_write_40x_pit (void *opaque, int sprn, int gprn)

{

    gen_helper_store_40x_pit(cpu_gpr[gprn]);

}

static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)

{

    DisasContext *ctx = opaque;

    gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);

    /* We must stop translation as we may have rebooted */

    gen_stop_exception(ctx);

}

static void spr_write_40x_sler (void *opaque, int sprn, int gprn)

{

    gen_helper_store_40x_sler(cpu_gpr[gprn]);

}

static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)

{

    gen_helper_store_booke_tcr(cpu_gpr[gprn]);

}

static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)

{

    gen_helper_store_booke_tsr(cpu_gpr[gprn]);

}

#endif

/* PowerPC 403 specific registers */

/* PBL1 / PBU1 / PBL2 / PBU2 */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_403_pbr (void *opaque, int gprn, int sprn)

{

    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));

}

static void spr_write_403_pbr (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);

    gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);

    tcg_temp_free_i32(t0);

}

static void spr_write_pir (void *opaque, int sprn, int gprn)

{

    TCGv t0 = tcg_temp_new();

    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);

    gen_store_spr(SPR_PIR, t0);

    tcg_temp_free(t0);

}

#endif

/* SPE specific registers */

static void spr_read_spefscr (void *opaque, int gprn, int sprn)

{

    TCGv_i32 t0 = tcg_temp_new_i32();

    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));

    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);

    tcg_temp_free_i32(t0);

}

static void spr_write_spefscr (void *opaque, int sprn, int gprn)

{

    TCGv_i32 t0 = tcg_temp_new_i32();

    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);

    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));

    tcg_temp_free_i32(t0);

}

#if !defined(CONFIG_USER_ONLY)

/* Callback used to write the exception vector base */

static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)

{

    TCGv t0 = tcg_temp_new();

    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));

    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);

    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));

    gen_store_spr(sprn, t0);

    tcg_temp_free(t0);

}

static void spr_write_excp_vector (void *opaque, int sprn, int gprn)

{

    DisasContext *ctx = opaque;

    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {

        TCGv t0 = tcg_temp_new();

        tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));

        tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);

        tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));

        gen_store_spr(sprn, t0);

        tcg_temp_free(t0);

    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {

        TCGv t0 = tcg_temp_new();

        tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));

        tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);

        tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));

        gen_store_spr(sprn, t0);

        tcg_temp_free(t0);

    } else {

        printf("Trying to write an unknown exception vector %d %03x\n",

               sprn, sprn);

        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);

    }

}

#endif

static inline void vscr_init (CPUPPCState *env, uint32_t val)

{

    env->vscr = val;

    /* Altivec always uses round-to-nearest */

    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);

    set_flush_to_zero(vscr_nj, &env->vec_status);

}

#if defined(CONFIG_USER_ONLY)

#define spr_register(env, num, name, uea_read, uea_write,                     \

                     oea_read, oea_write, initial_value)                      \

do {                                                                          \

     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \

} while (0)

static inline void _spr_register (CPUPPCState *env, int num,

                                  const char *name,

                                  void (*uea_read)(void *opaque, int gprn, int sprn),

                                  void (*uea_write)(void *opaque, int sprn, int gprn),

                                  target_ulong initial_value)

#else

static inline void spr_register (CPUPPCState *env, int num,

                                 const char *name,

                                 void (*uea_read)(void *opaque, int gprn, int sprn),

                                 void (*uea_write)(void *opaque, int sprn, int gprn),

                                 void (*oea_read)(void *opaque, int gprn, int sprn),

                                 void (*oea_write)(void *opaque, int sprn, int gprn),

                                 target_ulong initial_value)

#endif

{

    ppc_spr_t *spr;

    spr = &env->spr_cb[num];

    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||

#if !defined(CONFIG_USER_ONLY)

        spr->oea_read != NULL || spr->oea_write != NULL ||

#endif

        spr->uea_read != NULL || spr->uea_write != NULL) {

        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);

        exit(1);

    }

#if defined(PPC_DEBUG_SPR)

    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,

           name, initial_value);

#endif

    spr->name = name;

    spr->uea_read = uea_read;

    spr->uea_write = uea_write;

#if !defined(CONFIG_USER_ONLY)

    spr->oea_read = oea_read;

    spr->oea_write = oea_write;

#endif

    env->spr[num] = initial_value;

}

/* Generic PowerPC SPRs */

static void gen_spr_generic (CPUPPCState *env)

{

    /* Integer processing */

    spr_register(env, SPR_XER, "XER",

                 &spr_read_xer, &spr_write_xer,

                 &spr_read_xer, &spr_write_xer,

                 0x00000000);

    /* Branch contol */

    spr_register(env, SPR_LR, "LR",

                 &spr_read_lr, &spr_write_lr,

                 &spr_read_lr, &spr_write_lr,

                 0x00000000);

    spr_register(env, SPR_CTR, "CTR",

                 &spr_read_ctr, &spr_write_ctr,

                 &spr_read_ctr, &spr_write_ctr,

                 0x00000000);

    /* Interrupt processing */

    spr_register(env, SPR_SRR0, "SRR0",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SRR1, "SRR1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Processor control */

    spr_register(env, SPR_SPRG0, "SPRG0",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG1, "SPRG1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG2, "SPRG2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG3, "SPRG3",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* SPR common to all non-embedded PowerPC, including 601 */

static void gen_spr_ne_601 (CPUPPCState *env)

{

    /* Exception processing */

    spr_register(env, SPR_DSISR, "DSISR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_DAR, "DAR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Timer */

    spr_register(env, SPR_DECR, "DECR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_decr, &spr_write_decr,

                 0x00000000);

    /* Memory management */

    spr_register(env, SPR_SDR1, "SDR1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_sdr1, &spr_write_sdr1,

                 0x00000000);

}

/* BATs 0-3 */

static void gen_low_BATs (CPUPPCState *env)

{

#if !defined(CONFIG_USER_ONLY)

    spr_register(env, SPR_IBAT0U, "IBAT0U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT0L, "IBAT0L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_IBAT1U, "IBAT1U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT1L, "IBAT1L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_IBAT2U, "IBAT2U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT2L, "IBAT2L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_IBAT3U, "IBAT3U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT3L, "IBAT3L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_DBAT0U, "DBAT0U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT0L, "DBAT0L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    spr_register(env, SPR_DBAT1U, "DBAT1U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT1L, "DBAT1L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    spr_register(env, SPR_DBAT2U, "DBAT2U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT2L, "DBAT2L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    spr_register(env, SPR_DBAT3U, "DBAT3U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT3L, "DBAT3L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    env->nb_BATs += 4;

#endif

}

/* BATs 4-7 */

static void gen_high_BATs (CPUPPCState *env)

{

#if !defined(CONFIG_USER_ONLY)

    spr_register(env, SPR_IBAT4U, "IBAT4U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT4L, "IBAT4L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_IBAT5U, "IBAT5U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT5L, "IBAT5L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_IBAT6U, "IBAT6U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT6L, "IBAT6L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_IBAT7U, "IBAT7U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT7L, "IBAT7L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT4U, "DBAT4U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT4L, "DBAT4L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT5U, "DBAT5U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT5L, "DBAT5L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT6U, "DBAT6U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT6L, "DBAT6L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT7U, "DBAT7U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT7L, "DBAT7L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    env->nb_BATs += 4;

#endif

}

/* Generic PowerPC time base */

static void gen_tbl (CPUPPCState *env)

{

    spr_register(env, SPR_VTBL,  "TBL",

                 &spr_read_tbl, SPR_NOACCESS,

                 &spr_read_tbl, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_TBL,   "TBL",

                 &spr_read_tbl, SPR_NOACCESS,

                 &spr_read_tbl, &spr_write_tbl,

                 0x00000000);

    spr_register(env, SPR_VTBU,  "TBU",

                 &spr_read_tbu, SPR_NOACCESS,

                 &spr_read_tbu, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_TBU,   "TBU",

                 &spr_read_tbu, SPR_NOACCESS,

                 &spr_read_tbu, &spr_write_tbu,

                 0x00000000);

}

/* Softare table search registers */

static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)

{

#if !defined(CONFIG_USER_ONLY)

    env->nb_tlb = nb_tlbs;

    env->nb_ways = nb_ways;

    env->id_tlbs = 1;

    spr_register(env, SPR_DMISS, "DMISS",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_DCMP, "DCMP",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_HASH1, "HASH1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_HASH2, "HASH2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_IMISS, "IMISS",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_ICMP, "ICMP",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_RPA, "RPA",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

#endif

}

/* SPR common to MPC755 and G2 */

static void gen_spr_G2_755 (CPUPPCState *env)

{

    /* SGPRs */

    spr_register(env, SPR_SPRG4, "SPRG4",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG5, "SPRG5",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);