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# Date Author Comment
630ecca0 02/16/2011 04:35 pm Tristan Gingold

Handle icount for powerpc tbl/tbu/decr load and store.

Handle option '-icount X' on powerpc targets.

Signed-off-by: Tristan Gingold <>
Signed-off-by: Edgar E. Iglesias <>

9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...

95070372 09/30/2010 07:53 pm Edgar E. Iglesias

powerpc: Add a ppc-440x5 Xilinx model

Add a powerpc 440x5 with the model ID on the Xilinx virtex5.
Connect the 440x5 to the 40x interrupt logic.

Signed-off-by: Edgar E. Iglesias <>
Signed-off-by: Alexander Graf <>

488243b0 07/19/2010 01:33 am Aurelien Jarno

target-ppc: fix power mode checking on 7400/7410

Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC
7400 and 7410 support it.

de6a1dec 03/27/2010 12:37 am Dmitry Ilyevsky

target-ppc: generic PowerPC TBL

Time base SPRs TBL/TBU should be accessible in user/priv modes for reading
as specified in POWER ISA documentation. Therefore SPRs permissions were
changed in gen_tbl function.

Signed-off-by: Dmitry Ilyevsky <>...

74d77cae 10/18/2009 05:15 pm Thomas Monjalon

target-ppc: simpler definitions for microcontrollers based on e300

No need to alias e300 core for each CPU package.
Differences between microcontrollers have to be implemented in a higher layer
than translate_init.c

Signed-off-by: Thomas Monjalon <>...

492d7bf5 10/18/2009 05:15 pm Thomas Monjalon

target-ppc: add declarations of microcontrollers based on e300

Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.

Signed-off-by: Thomas Monjalon <>
Signed-off-by: Aurelien Jarno <>

8daf1781 10/18/2009 05:15 pm Thomas Monjalon

target-ppc: better support of e300 CPU core

Declare HID2 register.

Use high BATs for e300 (8 instead of 4).

Fix index of high BATs registers.
Before the fix, IBAT4-7 were overwriting IBAT0-3.

Signed-off-by: Fran├žois Armand <>
Signed-off-by: Aurelien Jarno <>

c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>

90e189ec 08/16/2009 02:13 pm Blue Swirl

Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx

Signed-off-by: Blue Swirl <>

e2542fe2 07/27/2009 10:09 pm Juan Quintela

rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

f4078236 07/13/2009 02:58 am Baojun Wang

target-ppc: enable PPC_MFTB for 44x

According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a
preserved instruction:

PPC440_UM2013.pdf, p.445, table A-3

when I compile a kernel (2.6.30, bamboo_defconfig/440EP &
canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump...

a139aa17 06/23/2009 08:11 pm Nathan Froyd

target-ppc: permit linux-user to read PVR

Access to the PVR SPR is normally forbidden from userspace apps. The
Linux kernel, however, fixes up reads in the appropriate trap handler.
To permit applications that read PVR to run on QEMU, then, we need to
implement the same handling of PVR reads....

5c55ff99 06/17/2009 06:22 pm Blue Swirl

Replace ELF section hack with normal table

Signed-off-by: Blue Swirl <>

c29b735c 05/16/2009 12:36 am Nathan Froyd

target-ppc: expose cpu capability flags

Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

2d3eb7bf 04/28/2009 09:07 pm Tristan Gingold

Fix powerpc 604 reset vector

According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is set
for hreset and the vector is at offset 0x100 from the exception prefix.

No difference in this area between 604 and 604e.

Signed-off-by: Tristan Gingold <>

fc1c67bc 04/28/2009 09:00 pm Blue Swirl

Fix PPC reset

515e2f7e 03/10/2009 09:37 pm aurel32

target-ppc: fix commit r6789

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162

69bd5820 03/09/2009 08:27 am aurel32

target-ppc: free a tcg temp variable

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162

d34defbc 03/09/2009 08:27 am aurel32

target-ppc: add support for reading/writing spefscr

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162

70976a79 03/08/2009 12:00 am aurel32

Fix off-by-one errors for Altivec and SPE registers

Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width. The QEMU GDB stub code would...

8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...

4e98d8cf 03/07/2009 10:54 pm blueswir1

Nop some SPRs on 970fx

Linux tries to access some SPRs on PPC64 boot. Let's just ignore those
for the 970fx for now to make it happy.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162

0cfe11ea 03/03/2009 08:12 am aurel32

target-ppc: improve mfcr/mtcrf

- use ctz32 instead of ffs - 1
- small optimisation of mtcrf
- add the name of both opcodes

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162

9fdc60bf 03/02/2009 06:42 pm aurel32

kvm/powerpc: Add irq support for E500 core

Signed-off-by: Liu Yu <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162

2adab7d6 02/28/2009 08:39 pm blueswir1

Implement HIOR

A real 970 CPU starts up with HIOR=0xfff00000 and triggers a reset
exception, basically ending up at IP 0xfff001000.

Later on this HIOR has to be set to 0 by the firmware in order to
enable the OS to handle interrupts on its own.

This patch maps HIOR to exec_prefix, which does the same thing...

bd5ea513 02/09/2009 06:50 pm aurel32

target-ppc: Model e500v{1,2} CPUs more accurately

The e500v1 chips only have single-precision floating point; don't say we
support the double-precision floating-point instructions on such chips.
Also add an e500v1 -cpu argument for a generic e500v1.

Signed-off-by: Nathan Froyd <>...

40569b7e 02/09/2009 06:49 pm aurel32

target-ppc: Model SPE floating-point instructions more accurately

Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.

Signed-off-by: Nathan Froyd <>...

0d0266a5 02/06/2009 12:06 am aliguori

targets: remove error handling from qemu_malloc() callers (Avi Kivity)

Signed-off-by: Avi Kivity <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162

cf8358c8 02/03/2009 09:55 pm aurel32

Add calls to initialize VSCR on appropriate machines

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162

688890f7 01/24/2009 05:08 pm aurel32

target-ppc: Add SPE register read/write using XML

Don't read/write SPEFSCR until we figure out what to do about exceptions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162

b4f8d821 01/24/2009 05:08 pm aurel32

target-ppc: Add Altivec register read/write using XML

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162

24951522 01/24/2009 05:08 pm aurel32

target-ppc: Add float register read/write using XML

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162

4e47ea67 01/24/2009 05:07 pm aurel32

target-ppc: Include gdbstub.h

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6422 c046a42c-6fe2-441c-8c8c-71466251a162

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

b1503cda 12/22/2008 10:33 pm malc

Use the ARRAY_SIZE() macro where appropriate.

Change from v1:
Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162

e06fcd75 12/12/2008 12:42 am aurel32

target-ppc: rework exception code

... also remove two warnings.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162

45d827d2 12/07/2008 03:40 pm aurel32

target-ppc: convert SPR accesses to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162

cd390083 11/16/2008 03:53 pm blueswir1

Attached patch fixes a series of this warning
when compiling on NetBSD:

warning: array subscript has type 'char'

Signed-off-by: Christoph Egger <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5727 c046a42c-6fe2-441c-8c8c-71466251a162

3d7b417e 10/21/2008 02:28 pm aurel32

target-ppc: Convert XER accesses to TCG

Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162

b55266b5 09/20/2008 11:07 am blueswir1

Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162

cfdcd37a 09/14/2008 09:30 pm aurel32

ppc: Convert ctr, lr moves to TCG

Introduce TCG variables cpu_{ctr,lr} and replace op_{load,store}_{lr,ctr}
with tcg_gen_mov_tl.

Signed-off-by: Andreas Faerber <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5217 c046a42c-6fe2-441c-8c8c-71466251a162

79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162

4e777442 12/10/2007 09:40 am j_mayer

Fix PowerPC 74xx definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162

bd928eba 11/21/2007 03:08 pm j_mayer

Fix PowerPC 7xx definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162

082c6681 11/19/2007 03:22 pm j_mayer

Remove shared macro used to define PowerPC implementations instructions sets:
tend more to propagate bugged definition than simplify the code.
Check and fix PowerPC 6xx implementations definitions.
Misc fixes in PowerPC CPU list.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162

add78955 11/19/2007 01:41 pm j_mayer

PowerPC 620 MMU do not have the same exact behavior as standard
64 bits PowerPC ones.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162

4018bae9 11/19/2007 03:48 am j_mayer

New PowerPC CPU flag to define the decrementer and time-base source clock.
Use it to properly initialize the clock for the PreP target.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162

4c1b1bfe 11/18/2007 01:14 am j_mayer

Improve PowerPC instructions set dump.
Remove meaningless define from cpu.h
Misc cleanups.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162

80d11f44 11/18/2007 01:02 am j_mayer

Add definitions for Freescale PowerPC implementations,
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
thus providing a way of testing their implementation specific instructions.

...

b4095fed 11/18/2007 12:42 am j_mayer

Define Freescale cores specific MMU model, exceptions and input bus.
(but do not provide any actual implementation).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162

05332d70 11/18/2007 12:26 am j_mayer

A little more granularity in PowerPC instructions definition is needed
in order to implement Freescale cores.
Fix efsadd / efssub opcodes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162

7820dbf3 11/17/2007 04:16 am j_mayer

Make the PowerPC MMU model, exception model and input bus model
typedefed enums.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162

b172c56a 11/17/2007 03:37 am j_mayer

Always make all PowerPC exception definitions visible.
Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162

1b413d55 11/14/2007 03:08 am j_mayer

Reorganize PowerPC instructions categories, add icbi separate case.
Fix frsqrtes instruction opcode.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3636 c046a42c-6fe2-441c-8c8c-71466251a162

c3e36823 11/13/2007 01:40 am j_mayer

Add PVR and SPR definition for most embedded PowerPC from Freescale.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3632 c046a42c-6fe2-441c-8c8c-71466251a162

ee4e83ed 11/11/2007 01:51 am j_mayer

Allow selection of PowerPC CPU giving a PVR.
Remove unused pvr_mask field from CPU definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162

aaed909a 11/10/2007 05:15 pm bellard

added cpu_model parameter to cpu_init()

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162

056401ea 11/04/2007 04:55 am j_mayer

PowerPC 601 need specific callbacks for its BATs setup.
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation....

2e13d23a 11/03/2007 04:23 pm j_mayer

Fix PowerPC high BATs access: BAT number was incorrect.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3519 c046a42c-6fe2-441c-8c8c-71466251a162

faadf50e 11/03/2007 03:37 pm j_mayer PowerPC MMU and exception fixes:
  • PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than
    later PowerPC implementation.
  • Bugfix in BATs check: must not stop after 4 BATs when more are provided.
  • Enable POWER 'rac' instruction.
  • Fix exception prefix for all supported PowerPC implementations....
2f462816 10/26/2007 02:14 am j_mayer

Implement power-management for all defined PowerPC CPUs.
Fix PowerPC 970MP definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3440 c046a42c-6fe2-441c-8c8c-71466251a162

8ca3f6c3 10/26/2007 12:37 am j_mayer

Allow selection of all defined PowerPC 74xx (aka G4) CPUs.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3437 c046a42c-6fe2-441c-8c8c-71466251a162

a13d7523 10/14/2007 12:14 pm j_mayer

There is no need of a specific MMU model for PowerPC 601.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162

25ba3a68 10/08/2007 05:58 am j_mayer

Remove synonymous in PowerPC MSR bits definitions.
Fix MSR EP bit buggy definition.
Remove unuseful MSR flags.
Fix MSR bits and flags definitions for most supported PowerPC implementations.
Add MSR definitions/flags constistency checks and optional dump.
...

141c8ae2 10/08/2007 05:44 am j_mayer

Real-mode only PowerPC 40x do not have any TLBs.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3353 c046a42c-6fe2-441c-8c8c-71466251a162

4e80effc 10/08/2007 05:35 am j_mayer

Implement exception prefix feature for PowerPC 601.
Fix PowerPC 601 hardware reset vector.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3352 c046a42c-6fe2-441c-8c8c-71466251a162

7a3a6927 10/08/2007 05:23 am j_mayer

Add missing exception vectors for PowerPC 7x5.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3351 c046a42c-6fe2-441c-8c8c-71466251a162

417bf010 10/08/2007 02:10 am j_mayer

Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3350 c046a42c-6fe2-441c-8c8c-71466251a162

f2e63a42 10/07/2007 06:43 pm j_mayer

Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets....

d26bfc9a 10/07/2007 05:41 pm j_mayer

Add MSR bits signification per PowerPC implementation flags (to be continued).
As a side effect, single step and branch step are available again.
Remove irrelevant MSR bits definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162

12de9a39 10/06/2007 01:06 am j_mayer

Full implementation of PowerPC 64 MMU, just missing support for 1 TB
memory segments.
Remove the PowerPC 64 "bridge" MMU model and implement segment registers
emulation using SLB entries instead.
Make SLB area size implementation dependant.
Improve TLB & SLB search debug traces....

65f9ee8d 10/05/2007 04:11 pm j_mayer

Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3333 c046a42c-6fe2-441c-8c8c-71466251a162

1c27f8fb 10/05/2007 04:09 pm j_mayer

PowerPC hardware reset vector is now considered as part of the exception model.
Use it at CPU initialisation time.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3332 c046a42c-6fe2-441c-8c8c-71466251a162

e57448f1 10/04/2007 04:50 am j_mayer More cache tuning fixes:
  • fix the tunable cache line size probe for PowerPC 970.
  • initialize HID5 so cache line is 32 bytes long when running in user-mode only

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3322 c046a42c-6fe2-441c-8c8c-71466251a162

d63001d1 10/04/2007 03:51 am j_mayer

Make PowerPC cache line size implementation dependant.
Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162

06403421 10/03/2007 11:27 pm j_mayer

HID0 is a write-clear register on 970 (DBSR).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3320 c046a42c-6fe2-441c-8c8c-71466251a162

00af685f 10/03/2007 04:05 am j_mayer

We never have to export ppc_set_irq.
Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3316 c046a42c-6fe2-441c-8c8c-71466251a162

578bb252 10/01/2007 07:48 am j_mayer

More comments about unimplemented SPRs.
Tag unused functions with unused attribute instead of using #ifdef (TODO)
to ease tests: just have to enable the implementation in the cpu_defs table.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3306 c046a42c-6fe2-441c-8c8c-71466251a162

035feb88 10/01/2007 04:38 am j_mayer

Share more SPR instanciations between all PowerPC 401 incarnations.
Add comments about some unimplemented storage control dedicated SPRs.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3301 c046a42c-6fe2-441c-8c8c-71466251a162

6f5d427d 10/01/2007 04:32 am j_mayer

Implement embedded PowerPC exceptions prefix and vectors registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3300 c046a42c-6fe2-441c-8c8c-71466251a162

4e290a0b 10/01/2007 04:27 am j_mayer

Share input pins and internal interrupt controller between all PowerPC 40x.
Fix critical input interrupt generation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162

068abdc8 09/30/2007 05:52 pm j_mayer

Fix inconsistent end conditions in ppc_find_xxx functions.
(crash reported by Andreas Farber when using default CPU).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3293 c046a42c-6fe2-441c-8c8c-71466251a162

a062e36c 09/30/2007 03:38 am j_mayer

Implement the PowerPC alternate time-base, following the 2.04 specification.
Share most code with the time-base management routines.
Remove time-base write routines from user-mode emulation environments.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3277 c046a42c-6fe2-441c-8c8c-71466251a162

dee96f6c 09/29/2007 06:02 pm j_mayer

PowerPC emulation optimization:
avoid stopping translation after most SPR updates
when a context-synchronization instruction is also needed.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3265 c046a42c-6fe2-441c-8c8c-71466251a162

e1833e1f 09/29/2007 04:06 pm j_mayer Rework PowerPC exceptions model to make it more versatile:
  • don't use exception vectors as the exception number.
    Use vectors numbers as defined in the PowerPC embedded specification instead
    and extend this model to cover all emulated PowerPC variants exceptions....
237c0af0 09/29/2007 03:01 pm j_mayer

Define the proper bfd_mach to be used by the disassembler for each
PowerPC emulated CPU.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3257 c046a42c-6fe2-441c-8c8c-71466251a162

d12f4c38 09/29/2007 02:51 pm j_mayer

Change POWERPC_PPC_GENERIC to POWERPC_DEFAULT.
Use it as default for workstation targets.
Fix PowerPC 750fl and 750gl definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3256 c046a42c-6fe2-441c-8c8c-71466251a162

e3b98085 09/27/2007 03:48 pm ths

Build fix for PowerPC hosts, where "PPC" is a predefined macro name.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3251 c046a42c-6fe2-441c-8c8c-71466251a162

92a343da 09/27/2007 04:14 am j_mayer

New ppc64-linux-user target.
Allow use of PowerPC 970 for debugging (softmmu would not run, for now).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3246 c046a42c-6fe2-441c-8c8c-71466251a162

a750fc0b 09/27/2007 02:54 am j_mayer Great rework and cleanups to ease PowerPC implementations definitions.
  • cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
  • add new flags to define instructions sets more precisely
  • various changes in MMU models definitions
  • add definitions for PowerPC 440/460 support (insns and SPRs)....
2662a059 09/21/2007 08:50 am j_mayer

More PowerPC definitions, from POWER 2.04 specifications and misc sources.
Check that at least instructions set and SPRs are correct for
PowerPC 401, 403, 405 and 440 cores.
Implement PowerPC 401 MMU model (real-mode only).
Improve INSNs and SPRs dump to ease parse with standard shell tools....

36081602 09/17/2007 11:21 am j_mayer

Coding style fixes in PowerPC related code (no functional change):
- avoid useless blanks at EOL.
- avoid tabs.
- fix wrapping lines on 80 chars terminals.
- add missing ';' at macros EOL to avoid confusing auto-identers.
- fix identation.
- Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs)...

3b46e624 09/17/2007 11:09 am ths

find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162

5fafdf24 09/17/2007 12:08 am ths

find -type f | xargs sed -i 's/[\t ]$//g' # on most files

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162

5b284968 07/12/2007 03:18 am ths

Disable dead code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3071 c046a42c-6fe2-441c-8c8c-71466251a162

c294fc58 04/24/2007 09:44 am j_mayer

Improve PowerPC 405 MMU model / share more code for other embedded targets
support.
Fix PowerPC 405 MSR mask.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2717 c046a42c-6fe2-441c-8c8c-71466251a162

f9d6b6b0 04/19/2007 10:16 am j_mayer

Duplicated SPR fix for BookE PowerPC by Guglielmo Morandin

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2704 c046a42c-6fe2-441c-8c8c-71466251a162