Revision bb98fe42 fpu/softfloat-specialize.h
| b/fpu/softfloat-specialize.h | ||
|---|---|---|
| 52 | 52 |
*----------------------------------------------------------------------------*/ |
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typedef struct {
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flag sign; |
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bits64 high, low;
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uint64_t high, low;
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|
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} commonNaNT; |
| 57 | 57 |
|
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/*---------------------------------------------------------------------------- |
| ... | ... | |
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if ( float16_is_signaling_nan( a ) ) float_raise( float_flag_invalid STATUS_VAR ); |
| 121 | 121 |
z.sign = float16_val(a) >> 15; |
| 122 | 122 |
z.low = 0; |
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z.high = ((bits64) float16_val(a))<<54;
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z.high = ((uint64_t) float16_val(a))<<54;
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return z; |
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} |
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|
| ... | ... | |
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#if SNAN_BIT_IS_ONE |
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return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); |
| 158 | 158 |
#else |
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return ( 0xFF800000 <= (bits32) ( a<<1 ) );
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return ( 0xFF800000 <= (uint32_t) ( a<<1 ) );
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#endif |
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} |
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|
| ... | ... | |
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{
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uint32_t a = float32_val(a_); |
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#if SNAN_BIT_IS_ONE |
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return ( 0xFF800000 <= (bits32) ( a<<1 ) );
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return ( 0xFF800000 <= (uint32_t) ( a<<1 ) );
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#else |
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return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); |
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#endif |
| ... | ... | |
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# error Rules for silencing a signaling NaN are target-specific |
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# endif |
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#else |
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bits32 a = float32_val(a_);
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|
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uint32_t a = float32_val(a_);
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|
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a |= (1 << 22); |
| 195 | 195 |
return make_float32(a); |
| 196 | 196 |
#endif |
| ... | ... | |
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if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid STATUS_VAR ); |
| 212 | 212 |
z.sign = float32_val(a)>>31; |
| 213 | 213 |
z.low = 0; |
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z.high = ( (bits64) float32_val(a) )<<41;
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z.high = ( (uint64_t) float32_val(a) )<<41;
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return z; |
| 216 | 216 |
} |
| 217 | 217 |
|
| ... | ... | |
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|
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static float32 commonNaNToFloat32( commonNaNT a STATUS_PARAM) |
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{
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bits32 mantissa = a.high>>41;
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uint32_t mantissa = a.high>>41;
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|
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if ( STATUS(default_nan_mode) ) {
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return float32_default_nan; |
| ... | ... | |
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|
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if ( mantissa ) |
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return make_float32( |
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( ( (bits32) a.sign )<<31 ) | 0x7F800000 | ( a.high>>41 ) );
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( ( (uint32_t) a.sign )<<31 ) | 0x7F800000 | ( a.high>>41 ) );
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else |
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return float32_default_nan; |
| 236 | 236 |
} |
| ... | ... | |
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{
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flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; |
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flag aIsLargerSignificand; |
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bits32 av, bv;
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|
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uint32_t av, bv;
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aIsQuietNaN = float32_is_quiet_nan( a ); |
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aIsSignalingNaN = float32_is_signaling_nan( a ); |
| ... | ... | |
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if ( STATUS(default_nan_mode) ) |
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return float32_default_nan; |
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|
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if ((bits32)(av<<1) < (bits32)(bv<<1)) {
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if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
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aIsLargerSignificand = 0; |
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} else if ((bits32)(bv<<1) < (bits32)(av<<1)) {
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} else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
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aIsLargerSignificand = 1; |
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} else {
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aIsLargerSignificand = (av < bv) ? 1 : 0; |
| ... | ... | |
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|
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int float64_is_quiet_nan( float64 a_ ) |
| 396 | 396 |
{
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bits64 a = float64_val(a_);
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uint64_t a = float64_val(a_);
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#if SNAN_BIT_IS_ONE |
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return |
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( ( ( a>>51 ) & 0xFFF ) == 0xFFE ) |
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&& ( a & LIT64( 0x0007FFFFFFFFFFFF ) ); |
| 402 | 402 |
#else |
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return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) );
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return ( LIT64( 0xFFF0000000000000 ) <= (uint64_t) ( a<<1 ) );
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#endif |
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} |
| 406 | 406 |
|
| ... | ... | |
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int float64_is_signaling_nan( float64 a_ ) |
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{
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bits64 a = float64_val(a_);
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uint64_t a = float64_val(a_);
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#if SNAN_BIT_IS_ONE |
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return ( LIT64( 0xFFF0000000000000 ) <= (bits64) ( a<<1 ) );
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return ( LIT64( 0xFFF0000000000000 ) <= (uint64_t) ( a<<1 ) );
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#else |
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return |
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( ( ( a>>51 ) & 0xFFF ) == 0xFFE ) |
| ... | ... | |
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# error Rules for silencing a signaling NaN are target-specific |
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# endif |
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#else |
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bits64 a = float64_val(a_);
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uint64_t a = float64_val(a_);
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a |= LIT64( 0x0008000000000000 ); |
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return make_float64(a); |
| 442 | 442 |
#endif |
| ... | ... | |
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|
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static float64 commonNaNToFloat64( commonNaNT a STATUS_PARAM) |
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{
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bits64 mantissa = a.high>>12;
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uint64_t mantissa = a.high>>12;
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| 472 | 472 |
|
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if ( STATUS(default_nan_mode) ) {
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return float64_default_nan; |
| ... | ... | |
| 476 | 476 |
|
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if ( mantissa ) |
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return make_float64( |
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( ( (bits64) a.sign )<<63 )
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( ( (uint64_t) a.sign )<<63 )
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| LIT64( 0x7FF0000000000000 ) |
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| ( a.high>>12 )); |
| 482 | 482 |
else |
| ... | ... | |
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{
|
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flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; |
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flag aIsLargerSignificand; |
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bits64 av, bv;
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uint64_t av, bv;
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aIsQuietNaN = float64_is_quiet_nan( a ); |
| 499 | 499 |
aIsSignalingNaN = float64_is_signaling_nan( a ); |
| ... | ... | |
| 507 | 507 |
if ( STATUS(default_nan_mode) ) |
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return float64_default_nan; |
| 509 | 509 |
|
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if ((bits64)(av<<1) < (bits64)(bv<<1)) {
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if ((uint64_t)(av<<1) < (uint64_t)(bv<<1)) {
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aIsLargerSignificand = 0; |
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} else if ((bits64)(bv<<1) < (bits64)(av<<1)) {
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} else if ((uint64_t)(bv<<1) < (uint64_t)(av<<1)) {
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aIsLargerSignificand = 1; |
| 514 | 514 |
} else {
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aIsLargerSignificand = (av < bv) ? 1 : 0; |
| ... | ... | |
| 534 | 534 |
int floatx80_is_quiet_nan( floatx80 a ) |
| 535 | 535 |
{
|
| 536 | 536 |
#if SNAN_BIT_IS_ONE |
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bits64 aLow;
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uint64_t aLow;
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aLow = a.low & ~ LIT64( 0x4000000000000000 ); |
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return |
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( ( a.high & 0x7FFF ) == 0x7FFF ) |
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&& (bits64) ( aLow<<1 )
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&& (uint64_t) ( aLow<<1 )
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&& ( a.low == aLow ); |
| 544 | 544 |
#else |
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return ( ( a.high & 0x7FFF ) == 0x7FFF ) |
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&& (LIT64( 0x8000000000000000 ) <= ((bits64) ( a.low<<1 )));
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&& (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
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#endif |
| 548 | 548 |
} |
| 549 | 549 |
|
| ... | ... | |
| 557 | 557 |
{
|
| 558 | 558 |
#if SNAN_BIT_IS_ONE |
| 559 | 559 |
return ( ( a.high & 0x7FFF ) == 0x7FFF ) |
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&& (LIT64( 0x8000000000000000 ) <= ((bits64) ( a.low<<1 )));
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&& (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
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#else |
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bits64 aLow;
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uint64_t aLow;
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| 563 | 563 |
|
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aLow = a.low & ~ LIT64( 0x4000000000000000 ); |
| 565 | 565 |
return |
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( ( a.high & 0x7FFF ) == 0x7FFF ) |
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&& (bits64) ( aLow<<1 )
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&& (uint64_t) ( aLow<<1 )
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&& ( a.low == aLow ); |
| 569 | 569 |
#endif |
| 570 | 570 |
} |
| ... | ... | |
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z.low = a.high; |
| 629 | 629 |
else |
| 630 | 630 |
z.low = floatx80_default_nan_low; |
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z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
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z.high = ( ( (uint16_t) a.sign )<<15 ) | 0x7FFF;
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return z; |
| 633 | 633 |
} |
| 634 | 634 |
|
| ... | ... | |
| 689 | 689 |
&& ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) ); |
| 690 | 690 |
#else |
| 691 | 691 |
return |
| 692 |
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
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| 692 |
( LIT64( 0xFFFE000000000000 ) <= (uint64_t) ( a.high<<1 ) )
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| 693 | 693 |
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) ); |
| 694 | 694 |
#endif |
| 695 | 695 |
} |
| ... | ... | |
| 703 | 703 |
{
|
| 704 | 704 |
#if SNAN_BIT_IS_ONE |
| 705 | 705 |
return |
| 706 |
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
|
|
| 706 |
( LIT64( 0xFFFE000000000000 ) <= (uint64_t) ( a.high<<1 ) )
|
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| 707 | 707 |
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) ); |
| 708 | 708 |
#else |
| 709 | 709 |
return |
| ... | ... | |
| 767 | 767 |
} |
| 768 | 768 |
|
| 769 | 769 |
shift128Right( a.high, a.low, 16, &z.high, &z.low ); |
| 770 |
z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF000000000000 );
|
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| 770 |
z.high |= ( ( (uint64_t) a.sign )<<63 ) | LIT64( 0x7FFF000000000000 );
|
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| 771 | 771 |
return z; |
| 772 | 772 |
} |
| 773 | 773 |
|
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