Revision bba5ed77 hw/pcie_port.c

b/hw/pcie_port.c
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    pci_set_word(d->config + PCI_STATUS, 0);
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    pci_set_word(d->config + PCI_SEC_STATUS, 0);
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    /* Unlike conventional pci bridge, some bits are hardwared to 0. */


  		





  
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    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,


  		





  
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                 PCI_BRIDGE_CTL_PARITY |


  		





  
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                 PCI_BRIDGE_CTL_ISA |


  		





  
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                 PCI_BRIDGE_CTL_VGA |


  		





  
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                 PCI_BRIDGE_CTL_SERR |


  		





  
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                 PCI_BRIDGE_CTL_BUS_RESET);


  		





  
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    /* 7.5.3.5 Prefetchable Memory Base Limit


  		





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     * The Prefetchable Memory Base and Prefetchable Memory Limit registers


  		





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     * must indicate that 64-bit addresses are supported, as defined in


  		












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