Archipelago » qemu

void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);

int kbd_mouse_is_absolute(void);

    /* Touchscreen resolution */

    int x;

    int y;

#include "devices.h"

#include "console.h"

    qemu_irq interrupt;

    int input[8];

#define ADS_Z1POS(x, y)	600

#define ADS_Z2POS(x, y)	(600 + 6000 / ADS_XPOS(x, y))

{

    if (s->interrupt)

        qemu_set_irq(s->interrupt, s->pressure == 0);

uint32_t ads7846_read(void *opaque)

{

    return s->output;

}

void ads7846_write(void *opaque, uint32_t value)

{

    switch (s->cycle ++) {

    case 0:

static void ads7846_ts_event(void *opaque,

                int x, int y, int z, int buttons_state)

{

    if (buttons_state) {

        x = 0x7fff - x;

static void ads7846_save(QEMUFile *f, void *opaque)

{

    int i;

    for (i = 0; i < 8; i ++)

static int ads7846_load(QEMUFile *f, void *opaque, int version_id)

{

    int i;

    for (i = 0; i < 8; i ++)

    return 0;

}

{

    s->interrupt = penirq;

struct nand_state_t

{

    unsigned int rdy:1;

    unsigned int ale:1;

    unsigned int cle:1;

typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);

    uint8_t reg;

    uint32_t addr;

    int swallow;

        int pitch;

        blizzard_fn_t line_fn;

    } data;

/* Bytes(!) per pixel */

static const int blizzard_iformat_bpp[0x10] = {

    *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);

}

{

    uint8_t *src, *dst;

    int bypp[2];

        fn(dst, src, bypl[2]);

}

{

    if (s->source > 3 || !s->bpp ||

                    s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0])

    return 1;

}

{

    s->reg = 0;

    s->swallow = 0;

}

static inline void blizzard_invalidate_display(void *opaque) {

    s->invalidate = 1;

}

static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)

{

    switch (reg) {

    case 0x00:	/* Revision Code */

static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)

{

    switch (reg) {

    case 0x04:	/* PLL M-Divider */

uint16_t s1d13745_read(void *opaque, int dc)

{

    uint16_t value = blizzard_reg_read(s, s->reg);

    if (s->swallow -- > 0)

void s1d13745_write(void *opaque, int dc, uint16_t value)

{

    if (s->swallow -- > 0)

        return;

void s1d13745_write_block(void *opaque, int dc,

                void *buf, size_t len, int pitch)

{

    while (len > 0) {

        if (s->reg == 0x90 && dc &&

static void blizzard_update_display(void *opaque)

{

    int y, bypp, bypl, bwidth;

    uint8_t *src, *dst;

}

static void blizzard_screen_dump(void *opaque, const char *filename) {

    blizzard_update_display(opaque);

    if (s && ds_get_data(s->state))

void *s1d13745_init(qemu_irq gpio_int)

{

    s->fb = qemu_malloc(0x180000);

//#define DEBUG

    int sel;

    int dat;

        cbus_value,

    } cycle;

{

    if (s->slave[s->addr])

        s->slave[s->addr]->io(s->slave[s->addr]->opaque,

        hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);

}

{

    switch (s->cycle) {

    case cbus_address:

static void cbus_clk(void *opaque, int line, int level)

{

    if (!s->sel && level && !s->clk) {

        if (s->dir)

static void cbus_dat(void *opaque, int line, int level)

{

    s->dat = level;

}

static void cbus_sel(void *opaque, int line, int level)

{

    if (!level) {

        s->dir = 1;

    s->sel = level;

}

{

    s->dat_out = dat;

    s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0];

    return &s->cbus;

}

{

    s->slave[slave->addr] = slave;

}

/* Retu/Vilma */

    uint16_t irqst;

    uint16_t irqen;

    uint16_t cc[2];

    int is_vilma;

    qemu_irq irq;

{

    qemu_set_irq(s->irq, s->irqst & ~s->irqen);

}

    retu_adc_self_temp	= 13,	/* RETU temperature */

};

{

#ifdef DEBUG

    printf("RETU read at %02x\n", reg);

    }

}

{

#ifdef DEBUG

    printf("RETU write of %04x at %02x\n", val, reg);

static void retu_io(void *opaque, int rw, int reg, uint16_t *val)

{

    if (rw)

        *val = retu_read(s, reg);

void *retu_init(qemu_irq irq, int vilma)

{

    s->irq = irq;

    s->irqen = 0xffff;

void retu_key_event(void *retu, int state)

{

    s->irqst |= 1 << retu_int_pwr;

    retu_interrupt_update(s);

#if 0

static void retu_head_event(void *retu, int state)

{

    if ((s->cc[0] & 0x500) == 0x500) {	/* TODO: Which bits? */

        /* TODO: reissue the interrupt every 100ms or so.  */

static void retu_hook_event(void *retu, int state)

{

    if ((s->cc[0] & 0x500) == 0x500) {

        /* TODO: reissue the interrupt every 100ms or so.  */

#endif

/* Tahvo/Betty */

    uint16_t irqst;

    uint16_t irqen;

    uint8_t charger;

    int is_betty;

    qemu_irq irq;

{

    qemu_set_irq(s->irq, s->irqst & ~s->irqen);

}

#define TAHVO_REG_NOPR		0x0c	/* (RW) Number of periods */

#define TAHVO_REG_FRR		0x0d	/* (RO) FR */

{

#ifdef DEBUG

    printf("TAHVO read at %02x\n", reg);

    }

}

{

#ifdef DEBUG

    printf("TAHVO write of %04x at %02x\n", val, reg);

static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val)

{

    if (rw)

        *val = tahvo_read(s, reg);

void *tahvo_init(qemu_irq irq, int betty)

{

    s->irq = irq;

    s->irqen = 0xffff;

void *ssd0323_init(qemu_irq *cmd_p);

/* ads7846.c */

uint32_t ads7846_read(void *opaque);

void ads7846_write(void *opaque, uint32_t value);

/* tsc210x.c */

                qemu_irq dav, AudioState *audio);

uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);

/* tsc2005.c */

void *tsc2005_init(qemu_irq pintdav);

uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);

/* stellaris_input.c */

void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);

uint16_t s1d13745_read(void *opaque, int dc);

/* cbus.c */

    qemu_irq clk;

    qemu_irq dat;

    qemu_irq sel;

void *retu_init(qemu_irq irq, int vilma);

void *tahvo_init(qemu_irq irq, int betty);

void retu_key_event(void *retu, int state);

/* tusb6010.c */

/* tc6393xb.c */

#define TC6393XB_RAM	0x110000 /* amount of ram for Video and USB */

                    qemu_irq handler);

/* sm501.c */

void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,

};

/* Update ECC parity count.  */

{

    uint8_t idx = nand_ecc_precalc_table[sample];

}

/* Reinitialise the counters.  */

{

    s->lp[0] = 0x0000;

    s->lp[1] = 0x0000;

}

/* Save/restore */

{

    qemu_put_8s(f, &s->cp);

    qemu_put_be16s(f, &s->lp[0]);

    qemu_put_be16s(f, &s->count);

}

{

    qemu_get_8s(f, &s->cp);

    qemu_get_be16s(f, &s->lp[0]);

                                uint16_t unlock_addr0, uint16_t unlock_addr1);

/* nand.c */

                int cle, int ale, int ce, int wp, int gnd);

#define NAND_MFR_TOSHIBA	0x98

#define NAND_MFR_SAMSUNG	0xec

void *onenand_raw_otp(void *opaque);

/* ecc.c */

    uint8_t cp;		/* Column parity */

    uint16_t lp[2];	/* Line parity */

    uint16_t count;

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

    int index;

    uint32_t connex_rom = 0x01000000;

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

    int index;

    uint32_t verdex_rom = 0x02000000;

void i2c_slave_load(QEMUFile *f, i2c_slave *dev);

/* max111x.c */

uint32_t max111x_read(void *opaque);

void max111x_write(void *opaque, uint32_t value);

/* max7310.c */

i2c_slave *max7310_init(i2c_bus *bus);

#define METADATA_SIZE	0x20

/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */

    IDEState ide[2];

    uint32_t attr_base;

    uint32_t io_base;

    uint8_t ctrl;

    uint16_t io;

    int cycle;

/* Register bitfields */

enum md_opt {

    CTRL_SRST		= 0x04,

};

{

    if (!s->card.slot)

        return;

static void md_set_irq(void *opaque, int irq, int level)

{

    if (level)

        s->stat |= STAT_INT;

    else

    md_interrupt_update(s);

}

{

    s->opt = OPT_MODE_MMAP;

    s->stat = 0;

static uint8_t md_attr_read(void *opaque, uint32_t at)

{

    if (at < s->attr_base) {

        if (at < s->card.cis_len)

            return s->card.cis[at];

static void md_attr_write(void *opaque, uint32_t at, uint8_t value)

{

    at -= s->attr_base;

    switch (at) {

static uint16_t md_common_read(void *opaque, uint32_t at)

{

    uint16_t ret;

    at -= s->io_base;

static void md_common_write(void *opaque, uint32_t at, uint16_t value)

{

    at -= s->io_base;

    switch (s->opt & OPT_MODE) {

static void md_save(QEMUFile *f, void *opaque)

{

    int i;

    uint8_t drive1_selected;

static int md_load(QEMUFile *f, void *opaque, int version_id)

{

    int i;

    uint8_t drive1_selected;

static int dscm1xxxx_attach(void *opaque)

{

    md->card.attr_read = md_attr_read;

    md->card.attr_write = md_attr_write;

    md->card.common_read = md_common_read;

static int dscm1xxxx_detach(void *opaque)

{

    md_reset(md);

    return 0;

}

{

    md->card.state = md;

    md->card.attach = dscm1xxxx_attach;

    md->card.detach = dscm1xxxx_detach;

#include "qemu-timer.h"

#include "console.h"

    i2c_slave i2c;

    int i2c_dir;

    int i2c_cycle;

        uint8_t addr[3];

        QEMUTimer *tm[3];

    } pwm;

#define INT_KEYPAD		(1 << 0)

#define INT_ERROR		(1 << 3)

#define ERR_KEYOVR		(1 << 2)

#define ERR_FIFOOVR		(1 << 6)

{

    qemu_set_irq(s->nirq, !s->status);

}

{

}

{

    s->config = 0x80;

    s->status = INT_NOINIT;

    lm_kbd_gpio_update(s);

}

{

    s->error |= err;

    s->status |= INT_ERROR;

    lm_kbd_irq_update(s);

}

{

}

{

    lm_kbd_pwm_tick(s, line);

}

#define LM832x_MAX_KPX		8

#define LM832x_MAX_KPY		12

{

    int ret;

    return ret >> (byte << 3);

}

{

    switch (reg) {

    case LM832x_CMD_WRITE_CFG:

static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event)

{

    switch (event) {

    case I2C_START_RECV:

static int lm_i2c_rx(i2c_slave *i2c)

{

    return lm_kbd_read(s, s->reg, s->i2c_cycle ++);

}

static int lm_i2c_tx(i2c_slave *i2c, uint8_t data)

{

    if (!s->i2c_cycle)

        s->reg = data;

static void lm_kbd_save(QEMUFile *f, void *opaque)

{

    int i;

    i2c_slave_save(f, &s->i2c);

static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id)

{

    int i;

    i2c_slave_load(f, &s->i2c);

    return 0;

}

{

    s->model = 0x8323;

    s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s);

    s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s);

void lm832x_key_event(struct i2c_slave *i2c, int key, int state)

{

    if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))

        return;

{

    uint32_t sector_len = 256 * 1024;

    target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };

    qemu_irq *mst_irq;

    int i, index;

#define S1_IRQ        15

extern qemu_irq

#endif /* __MAINSTONE_H__ */

#include "hw.h"

#include "i2c.h"

    qemu_irq interrupt;

    uint8_t tb1, rb2, rb3;

    int cycle;

uint32_t max111x_read(void *opaque)

{

    if (!s->tb1)

        return 0;

/* Interpret a control-byte */

void max111x_write(void *opaque, uint32_t value)

{

    int measure, chan;

    /* Ignore the value if START bit is zero */

static void max111x_save(QEMUFile *f, void *opaque)

{

    int i;

    qemu_put_8s(f, &s->tb1);

static int max111x_load(QEMUFile *f, void *opaque, int version_id)

{

    int i;

    qemu_get_8s(f, &s->tb1);

    return 0;

}

{

    s->interrupt = cb;

    return s;

}

{

    s->inputs = 8;

    return s;

}

{

    s->inputs = 4;

    return s;

}

{

    if (line >= s->inputs) {

        printf("%s: There's no input %i\n", __FUNCTION__, line);

#include "hw.h"

#include "i2c.h"

    i2c_slave i2c;

    int i2c_command_byte;

    int len;

    uint8_t command;

    qemu_irq handler[8];

    qemu_irq *gpio_in;

void max7310_reset(i2c_slave *i2c)

{

    s->level &= s->direction;

    s->direction = 0xff;

    s->polarity = 0xf0;

static int max7310_rx(i2c_slave *i2c)

{

    switch (s->command) {

    case 0x00:	/* Input port */

static int max7310_tx(i2c_slave *i2c, uint8_t data)

{

    uint8_t diff;

    int line;

static void max7310_event(i2c_slave *i2c, enum i2c_event event)

{

    s->len = 0;

    switch (event) {

static void max7310_save(QEMUFile *f, void *opaque)

{

    qemu_put_be32(f, s->i2c_command_byte);

    qemu_put_be32(f, s->len);

static int max7310_load(QEMUFile *f, void *opaque, int version_id)

{

    s->i2c_command_byte = qemu_get_be32(f);

    s->len = qemu_get_be32(f);

static void max7310_gpio_set(void *opaque, int line, int level)

{

    if (line >= ARRAY_SIZE(s->handler) || line  < 0)

        hw_error("bad GPIO line");

/* MAX7310 is SMBus-compatible (can be used with only SMBus protocols),

 * but also accepts sequences that are not SMBus so return an I2C device.  */

{

    s->i2c.event = max7310_event;

    s->i2c.recv = max7310_rx;

    s->i2c.send = max7310_tx;

qemu_irq *max7310_gpio_in_get(i2c_slave *i2c)

{

    return s->gpio_in;

}

void max7310_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler)

{

    if (line >= ARRAY_SIZE(s->handler) || line  < 0)

        hw_error("bad GPIO line");

	return 0;

}

{

	mst_irq_state *s;

	int iomemtype;

# define MAX_PAGE		0x800

# define MAX_OOB		0x40

    uint8_t manf_id, chip_id;

    int size, pages;

    int page_shift, oob_shift, erase_shift, addr_shift;

    int status;

    int offset;

};

# define NAND_NO_AUTOINCR	0x00000001

# include "nand.c"

/* Information based on Linux drivers/mtd/nand/nand_ids.c */

    int size;

    int width;

    int page_shift;

    [0xc5] = { 2048,	16,	0, 0, LP_OPTIONS16 },

};

{

    s->cmd = NAND_CMD_READ0;

    s->addr = 0;

    s->status &= NAND_IOSTATUS_UNPROTCT;

}

{

    switch (s->cmd) {

    case NAND_CMD_READ0:

static void nand_save(QEMUFile *f, void *opaque)

{

    qemu_put_byte(f, s->cle);

    qemu_put_byte(f, s->ale);

    qemu_put_byte(f, s->ce);

static int nand_load(QEMUFile *f, void *opaque, int version_id)

{

    s->cle = qemu_get_byte(f);

    s->ale = qemu_get_byte(f);

    s->ce = qemu_get_byte(f);

 *

 * CE, WP and R/B are active low.

 */

                int cle, int ale, int ce, int wp, int gnd)

{

    s->cle = cle;

        s->status &= ~NAND_IOSTATUS_UNPROTCT;

}

{

    *rb = 1;

}

{

    if (!s->ce && s->cle) {

        if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {

    }

}

{

    int offset;

    return *(s->ioaddr ++);

}

{

    int pagesize;

    int index;

    if (nand_flash_ids[chip_id].size == 0) {

        hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);

    }

    index = drive_get_index(IF_MTD, 0, 0);

    if (index != -1)

        s->bdrv = drives_table[index].bdrv;

    return s;

}

{

    if (s->bdrv) {

        bdrv_close(s->bdrv);

#else

/* Program a single page */

{

    uint32_t off, page, sector, soff;

    uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];

}

/* Erase a single block */

{

    uint32_t i, page, addr;

    uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };

    }

}

                uint32_t addr, int offset)

{

    if (PAGE(addr) >= s->pages)

    s->addr += PAGE_SIZE;

}

{

    s->oob_shift = PAGE_SHIFT - 5;

    s->pages = s->size >> PAGE_SHIFT;

    struct {

        void *opaque;

        uint32_t (*txrx)(void *opaque, uint32_t value, int len);

    } ts;

    i2c_bus *i2c;

    int keymap[0x80];

    i2c_slave *kbd;

    void *retu;

    void *tahvo;

    void *nand;

}

/* Touchscreen and keypad controller */

    .x = 800,

    .y = 480,

    .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },

};

    .x = 800,

    .y = 480,

    .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },

    qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];

    qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];

    omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);

    omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);

{

    qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];

    qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];

    /* Using the NOR interface */

    omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,

qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);

void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);

    uint16_t (*receive)(void *opaque);

    void (*send)(void *opaque, uint16_t data);

    void *opaque;

struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,

                qemu_irq *irq, qemu_irq dma, omap_clk clk);

void omap_uwire_attach(struct omap_uwire_s *s,

struct omap_mcspi_s;

struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,

struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,

                qemu_irq *irq, omap_clk clk);

    void *opaque;