Revision bc24a225 hw/pxa.h
| b/hw/pxa.h | ||
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| 70 | 70 |
void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4); |
| 71 | 71 |
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| 72 | 72 |
/* pxa2xx_gpio.c */ |
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struct pxa2xx_gpio_info_s;
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struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
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typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
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PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
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| 75 | 75 |
CPUState *env, qemu_irq *pic, int lines); |
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qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
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void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
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qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s);
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void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
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| 78 | 78 |
int line, qemu_irq handler); |
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void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);
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void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler);
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| 80 | 80 |
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| 81 | 81 |
/* pxa2xx_dma.c */ |
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struct pxa2xx_dma_state_s;
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struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
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typedef struct PXA2xxDMAState PXA2xxDMAState;
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PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
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| 84 | 84 |
qemu_irq irq); |
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struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
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PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
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| 86 | 86 |
qemu_irq irq); |
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void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
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void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
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| 88 | 88 |
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| 89 | 89 |
/* pxa2xx_lcd.c */ |
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struct pxa2xx_lcdc_s;
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struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
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typedef struct PXA2xxLCDState PXA2xxLCDState;
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PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
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| 92 | 92 |
qemu_irq irq); |
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void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
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void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
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| 94 | 94 |
void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
| 95 | 95 |
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| 96 | 96 |
/* pxa2xx_mmci.c */ |
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struct pxa2xx_mmci_s;
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struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
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typedef struct PXA2xxMMCIState PXA2xxMMCIState;
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PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
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| 99 | 99 |
BlockDriverState *bd, qemu_irq irq, void *dma); |
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void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
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void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
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| 101 | 101 |
qemu_irq coverswitch); |
| 102 | 102 |
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| 103 | 103 |
/* pxa2xx_pcmcia.c */ |
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struct pxa2xx_pcmcia_s;
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struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
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int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
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typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
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int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
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| 107 | 107 |
int pxa2xx_pcmcia_dettach(void *opaque); |
| 108 | 108 |
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
| 109 | 109 |
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| ... | ... | |
| 112 | 112 |
int column; |
| 113 | 113 |
int row; |
| 114 | 114 |
}; |
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struct pxa2xx_keypad_s;
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struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
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typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
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PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
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| 117 | 117 |
qemu_irq irq); |
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void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map,
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void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
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| 119 | 119 |
int size); |
| 120 | 120 |
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| 121 | 121 |
/* pxa2xx.c */ |
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struct pxa2xx_ssp_s;
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void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
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typedef struct PXA2xxSSPState PXA2xxSSPState;
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void pxa2xx_ssp_attach(PXA2xxSSPState *port,
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| 124 | 124 |
uint32_t (*readfn)(void *opaque), |
| 125 | 125 |
void (*writefn)(void *opaque, uint32_t value), void *opaque); |
| 126 | 126 |
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struct pxa2xx_i2c_s;
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struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
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typedef struct PXA2xxI2CState PXA2xxI2CState;
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PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
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| 129 | 129 |
qemu_irq irq, uint32_t page_size); |
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i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);
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i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
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| 131 | 131 |
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struct pxa2xx_i2s_s;
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struct pxa2xx_fir_s;
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typedef struct PXA2xxI2SState PXA2xxI2SState;
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typedef struct PXA2xxFIrState PXA2xxFIrState;
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| 134 | 134 |
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struct pxa2xx_state_s {
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typedef struct {
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| 136 | 136 |
CPUState *env; |
| 137 | 137 |
qemu_irq *pic; |
| 138 | 138 |
qemu_irq reset; |
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struct pxa2xx_dma_state_s *dma;
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struct pxa2xx_gpio_info_s *gpio;
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struct pxa2xx_lcdc_s *lcd;
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struct pxa2xx_ssp_s **ssp;
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struct pxa2xx_i2c_s *i2c[2];
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struct pxa2xx_mmci_s *mmc;
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struct pxa2xx_pcmcia_s *pcmcia[2];
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struct pxa2xx_i2s_s *i2s;
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struct pxa2xx_fir_s *fir;
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struct pxa2xx_keypad_s *kp;
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PXA2xxDMAState *dma;
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PXA2xxGPIOInfo *gpio;
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PXA2xxLCDState *lcd;
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PXA2xxSSPState **ssp;
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PXA2xxI2CState *i2c[2];
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PXA2xxMMCIState *mmc;
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PXA2xxPCMCIAState *pcmcia[2];
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PXA2xxI2SState *i2s;
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PXA2xxFIrState *fir;
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PXA2xxKeyPadState *kp;
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| 149 | 149 |
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| 150 | 150 |
/* Power management */ |
| 151 | 151 |
target_phys_addr_t pm_base; |
| ... | ... | |
| 189 | 189 |
QEMUTimer *rtc_swal1; |
| 190 | 190 |
QEMUTimer *rtc_swal2; |
| 191 | 191 |
QEMUTimer *rtc_pi; |
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}; |
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} PXA2xxState;
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| 193 | 193 |
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struct pxa2xx_i2s_s {
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struct PXA2xxI2SState {
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qemu_irq irq; |
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struct pxa2xx_dma_state_s *dma;
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PXA2xxDMAState *dma;
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| 197 | 197 |
void (*data_req)(void *, int, int); |
| 198 | 198 |
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| 199 | 199 |
uint32_t control[2]; |
| ... | ... | |
| 215 | 215 |
# define PA_FMT "0x%08lx" |
| 216 | 216 |
# define REG_FMT "0x" TARGET_FMT_plx |
| 217 | 217 |
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struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision);
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struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size);
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PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
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PXA2xxState *pxa255_init(unsigned int sdram_size);
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| 220 | 220 |
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| 221 | 221 |
/* usb-ohci.c */ |
| 222 | 222 |
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, |
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