Revision bc24a225 hw/pxa2xx_lcd.c
| b/hw/pxa2xx_lcd.c | ||
|---|---|---|
| 15 | 15 |
#include "sysemu.h" |
| 16 | 16 |
#include "framebuffer.h" |
| 17 | 17 |
|
| 18 |
struct pxa2xx_lcdc_s {
|
|
| 18 |
struct PXA2xxLCDState {
|
|
| 19 | 19 |
qemu_irq irq; |
| 20 | 20 |
int irqlevel; |
| 21 | 21 |
|
| ... | ... | |
| 55 | 55 |
int up; |
| 56 | 56 |
uint8_t palette[1024]; |
| 57 | 57 |
uint8_t pbuffer[1024]; |
| 58 |
void (*redraw)(struct pxa2xx_lcdc_s *s, target_phys_addr_t addr,
|
|
| 58 |
void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
|
|
| 59 | 59 |
int *miny, int *maxy); |
| 60 | 60 |
|
| 61 | 61 |
target_phys_addr_t descriptor; |
| ... | ... | |
| 68 | 68 |
int orientation; |
| 69 | 69 |
}; |
| 70 | 70 |
|
| 71 |
struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
|
|
| 71 |
typedef struct __attribute__ ((__packed__)) {
|
|
| 72 | 72 |
uint32_t fdaddr; |
| 73 | 73 |
uint32_t fsaddr; |
| 74 | 74 |
uint32_t fidr; |
| 75 | 75 |
uint32_t ldcmd; |
| 76 |
}; |
|
| 76 |
} PXAFrameDescriptor;
|
|
| 77 | 77 |
|
| 78 | 78 |
#define LCCR0 0x000 /* LCD Controller Control register 0 */ |
| 79 | 79 |
#define LCCR1 0x004 /* LCD Controller Control register 1 */ |
| ... | ... | |
| 177 | 177 |
#define LDCMD_PAL (1 << 26) |
| 178 | 178 |
|
| 179 | 179 |
/* Route internal interrupt lines to the global IC */ |
| 180 |
static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
|
|
| 180 |
static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
|
|
| 181 | 181 |
{
|
| 182 | 182 |
int level = 0; |
| 183 | 183 |
level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); |
| ... | ... | |
| 197 | 197 |
} |
| 198 | 198 |
|
| 199 | 199 |
/* Set Branch Status interrupt high and poke associated registers */ |
| 200 |
static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
|
|
| 200 |
static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
|
|
| 201 | 201 |
{
|
| 202 | 202 |
int unmasked; |
| 203 | 203 |
if (ch == 0) {
|
| ... | ... | |
| 217 | 217 |
} |
| 218 | 218 |
|
| 219 | 219 |
/* Set Start Of Frame Status interrupt high and poke associated registers */ |
| 220 |
static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
|
|
| 220 |
static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
|
|
| 221 | 221 |
{
|
| 222 | 222 |
int unmasked; |
| 223 | 223 |
if (!(s->dma_ch[ch].command & LDCMD_SOFINT)) |
| ... | ... | |
| 240 | 240 |
} |
| 241 | 241 |
|
| 242 | 242 |
/* Set End Of Frame Status interrupt high and poke associated registers */ |
| 243 |
static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
|
|
| 243 |
static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
|
|
| 244 | 244 |
{
|
| 245 | 245 |
int unmasked; |
| 246 | 246 |
if (!(s->dma_ch[ch].command & LDCMD_EOFINT)) |
| ... | ... | |
| 263 | 263 |
} |
| 264 | 264 |
|
| 265 | 265 |
/* Set Bus Error Status interrupt high and poke associated registers */ |
| 266 |
static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
|
|
| 266 |
static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
|
|
| 267 | 267 |
{
|
| 268 | 268 |
s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER; |
| 269 | 269 |
if (s->irqlevel) |
| ... | ... | |
| 273 | 273 |
} |
| 274 | 274 |
|
| 275 | 275 |
/* Set Read Status interrupt high and poke associated registers */ |
| 276 |
static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
|
|
| 276 |
static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
|
|
| 277 | 277 |
{
|
| 278 | 278 |
s->status[0] |= LCSR0_RDST; |
| 279 | 279 |
if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) |
| ... | ... | |
| 281 | 281 |
} |
| 282 | 282 |
|
| 283 | 283 |
/* Load new Frame Descriptors from DMA */ |
| 284 |
static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
|
|
| 284 |
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
|
|
| 285 | 285 |
{
|
| 286 |
struct pxa_frame_descriptor_s desc;
|
|
| 286 |
PXAFrameDescriptor desc;
|
|
| 287 | 287 |
target_phys_addr_t descptr; |
| 288 | 288 |
int i; |
| 289 | 289 |
|
| ... | ... | |
| 315 | 315 |
|
| 316 | 316 |
static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
| 317 | 317 |
{
|
| 318 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 318 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 319 | 319 |
int ch; |
| 320 | 320 |
|
| 321 | 321 |
switch (offset) {
|
| ... | ... | |
| 409 | 409 |
static void pxa2xx_lcdc_write(void *opaque, |
| 410 | 410 |
target_phys_addr_t offset, uint32_t value) |
| 411 | 411 |
{
|
| 412 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 412 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 413 | 413 |
int ch; |
| 414 | 414 |
|
| 415 | 415 |
switch (offset) {
|
| ... | ... | |
| 572 | 572 |
}; |
| 573 | 573 |
|
| 574 | 574 |
/* Load new palette for a given DMA channel, convert to internal format */ |
| 575 |
static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
|
|
| 575 |
static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
|
|
| 576 | 576 |
{
|
| 577 | 577 |
int i, n, format, r, g, b, alpha; |
| 578 | 578 |
uint32_t *dest, *src; |
| ... | ... | |
| 663 | 663 |
} |
| 664 | 664 |
} |
| 665 | 665 |
|
| 666 |
static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
|
|
| 666 |
static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s,
|
|
| 667 | 667 |
target_phys_addr_t addr, int *miny, int *maxy) |
| 668 | 668 |
{
|
| 669 | 669 |
int src_width, dest_width; |
| ... | ... | |
| 690 | 690 |
fn, s->dma_ch[0].palette, miny, maxy); |
| 691 | 691 |
} |
| 692 | 692 |
|
| 693 |
static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
|
|
| 693 |
static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s,
|
|
| 694 | 694 |
target_phys_addr_t addr, int *miny, int *maxy) |
| 695 | 695 |
{
|
| 696 | 696 |
int src_width, dest_width; |
| ... | ... | |
| 718 | 718 |
miny, maxy); |
| 719 | 719 |
} |
| 720 | 720 |
|
| 721 |
static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
|
|
| 721 |
static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
|
|
| 722 | 722 |
{
|
| 723 | 723 |
int width, height; |
| 724 | 724 |
if (!(s->control[0] & LCCR0_ENB)) |
| ... | ... | |
| 740 | 740 |
|
| 741 | 741 |
static void pxa2xx_update_display(void *opaque) |
| 742 | 742 |
{
|
| 743 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 743 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 744 | 744 |
target_phys_addr_t fbptr; |
| 745 | 745 |
int miny, maxy; |
| 746 | 746 |
int ch; |
| ... | ... | |
| 807 | 807 |
|
| 808 | 808 |
static void pxa2xx_invalidate_display(void *opaque) |
| 809 | 809 |
{
|
| 810 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 810 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 811 | 811 |
s->invalidated = 1; |
| 812 | 812 |
} |
| 813 | 813 |
|
| ... | ... | |
| 818 | 818 |
|
| 819 | 819 |
static void pxa2xx_lcdc_orientation(void *opaque, int angle) |
| 820 | 820 |
{
|
| 821 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 821 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 822 | 822 |
|
| 823 | 823 |
if (angle) {
|
| 824 | 824 |
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert; |
| ... | ... | |
| 833 | 833 |
|
| 834 | 834 |
static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) |
| 835 | 835 |
{
|
| 836 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 836 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 837 | 837 |
int i; |
| 838 | 838 |
|
| 839 | 839 |
qemu_put_be32(f, s->irqlevel); |
| ... | ... | |
| 868 | 868 |
|
| 869 | 869 |
static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) |
| 870 | 870 |
{
|
| 871 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
|
|
| 871 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
| 872 | 872 |
int i; |
| 873 | 873 |
|
| 874 | 874 |
s->irqlevel = qemu_get_be32(f); |
| ... | ... | |
| 917 | 917 |
#define BITS 32 |
| 918 | 918 |
#include "pxa2xx_template.h" |
| 919 | 919 |
|
| 920 |
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
|
|
| 920 |
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
|
|
| 921 | 921 |
{
|
| 922 | 922 |
int iomemtype; |
| 923 |
struct pxa2xx_lcdc_s *s;
|
|
| 923 |
PXA2xxLCDState *s;
|
|
| 924 | 924 |
|
| 925 |
s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
|
|
| 925 |
s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState));
|
|
| 926 | 926 |
s->invalidated = 1; |
| 927 | 927 |
s->irq = irq; |
| 928 | 928 |
|
| ... | ... | |
| 976 | 976 |
return s; |
| 977 | 977 |
} |
| 978 | 978 |
|
| 979 |
void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
|
|
| 979 |
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
|
|
| 980 | 980 |
{
|
| 981 | 981 |
s->vsync_cb = handler; |
| 982 | 982 |
} |
Also available in: Unified diff