Revision bc24a225 hw/tc6393xb.c
b/hw/tc6393xb.c | ||
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78 | 78 |
#define NAND_MODE_ECC_READ 0x40 |
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#define NAND_MODE_ECC_RST 0x60 |
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struct tc6393xb_s {
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struct TC6393xbState {
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qemu_irq irq; |
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qemu_irq *sub_irqs; |
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struct { |
... | ... | |
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} nand; |
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int nand_enable; |
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uint32_t nand_phys; |
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struct nand_flash_s *flash;
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struct ecc_state_s ecc;
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NANDFlashState *flash;
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ECCState ecc;
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DisplayState *ds; |
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ram_addr_t vram_addr; |
... | ... | |
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blanked : 1; |
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}; |
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qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
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qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
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{ |
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return s->gpio_in; |
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} |
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static void tc6393xb_gpio_set(void *opaque, int line, int level) |
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{ |
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// struct tc6393xb_s *s = opaque;
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// TC6393xbState *s = opaque;
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if (line > TC6393XB_GPIOS) { |
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line); |
... | ... | |
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// FIXME: how does the chip reflect the GPIO input level change? |
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} |
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void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
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void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
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qemu_irq handler) |
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{ |
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if (line >= TC6393XB_GPIOS) { |
... | ... | |
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s->handler[line] = handler; |
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} |
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static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
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static void tc6393xb_gpio_handler_update(TC6393xbState *s)
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{ |
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uint32_t level, diff; |
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int bit; |
... | ... | |
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s->prev_level = level; |
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} |
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qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s)
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qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
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{ |
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return s->l3v; |
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} |
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static void tc6393xb_l3v(void *opaque, int line, int level) |
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{ |
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struct tc6393xb_s *s = opaque;
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TC6393xbState *s = opaque;
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s->blank = !level; |
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fprintf(stderr, "L3V: %d\n", level); |
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} |
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static void tc6393xb_sub_irq(void *opaque, int line, int level) { |
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struct tc6393xb_s *s = opaque;
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TC6393xbState *s = opaque;
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uint8_t isr = s->scr.ISR; |
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if (level) |
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isr |= 1 << line; |
... | ... | |
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case SCR_ ##N(1): return s->scr.N[1]; \ |
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case SCR_ ##N(2): return s->scr.N[2] |
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static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr)
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static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
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{ |
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switch (addr) { |
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case SCR_REVID: |
... | ... | |
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case SCR_ ##N(1): s->scr.N[1] = value; return; \ |
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case SCR_ ##N(2): s->scr.N[2] = value; return |
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static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value)
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static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
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{ |
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switch (addr) { |
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SCR_REG_B(ISR); |
... | ... | |
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#undef SCR_REG_L |
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#undef SCR_REG_A |
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static void tc6393xb_nand_irq(struct tc6393xb_s *s) {
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static void tc6393xb_nand_irq(TC6393xbState *s) {
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qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], |
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(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); |
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} |
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static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
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static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
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switch (addr) { |
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case NAND_CFG_COMMAND: |
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return s->nand_enable ? 2 : 0; |
... | ... | |
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fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); |
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return 0; |
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} |
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static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
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static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
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switch (addr) { |
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case NAND_CFG_COMMAND: |
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s->nand_enable = (value & 0x2); |
... | ... | |
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(uint32_t) addr, value & 0xff); |
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} |
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static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
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static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
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switch (addr) { |
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case NAND_DATA + 0: |
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case NAND_DATA + 1: |
... | ... | |
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fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); |
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return 0; |
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} |
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static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
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static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
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// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", |
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// (uint32_t) addr, value & 0xff); |
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switch (addr) { |
... | ... | |
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#define BITS 32 |
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#include "tc6393xb_template.h" |
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static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update)
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static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
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{ |
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switch (ds_get_bits_per_pixel(s->ds)) { |
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case 8: |
... | ... | |
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dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
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} |
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static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update)
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static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
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{ |
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int i, w; |
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uint8_t *d; |
... | ... | |
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static void tc6393xb_update_display(void *opaque) |
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{ |
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struct tc6393xb_s *s = opaque;
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TC6393xbState *s = opaque;
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int full_update; |
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if (s->scr_width == 0 || s->scr_height == 0) |
... | ... | |
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static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { |
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struct tc6393xb_s *s = opaque;
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TC6393xbState *s = opaque;
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switch (addr >> 8) { |
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case 0: |
... | ... | |
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} |
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static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { |
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struct tc6393xb_s *s = opaque;
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TC6393xbState *s = opaque;
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switch (addr >> 8) { |
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case 0: |
... | ... | |
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tc6393xb_writeb(opaque, addr + 3, value >> 24); |
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} |
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struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
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TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
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{ |
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int iomemtype; |
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struct tc6393xb_s *s;
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TC6393xbState *s;
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CPUReadMemoryFunc *tc6393xb_readfn[] = { |
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tc6393xb_readb, |
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tc6393xb_readw, |
... | ... | |
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tc6393xb_writel, |
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}; |
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s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
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s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState));
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s->irq = irq; |
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s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); |
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