Revision bc51c5c9
b/Changelog | ||
---|---|---|
18 | 18 |
- generic removable device support |
19 | 19 |
- support of CD-ROM change |
20 | 20 |
- multiple network interface support |
21 |
- initial x86-64 host support (Gwenole Beauchesne) |
|
21 | 22 |
|
22 | 23 |
version 0.5.2: |
23 | 24 |
|
b/Makefile.target | ||
---|---|---|
80 | 80 |
endif |
81 | 81 |
endif |
82 | 82 |
|
83 |
ifeq ($(ARCH),amd64) |
|
84 |
OP_CFLAGS=$(CFLAGS) -falign-functions=0 |
|
85 |
LDFLAGS+=-Wl,-T,$(SRC_PATH)/amd64.ld |
|
86 |
endif |
|
87 |
|
|
83 | 88 |
ifeq ($(ARCH),ppc) |
84 | 89 |
OP_CFLAGS=$(CFLAGS) |
85 | 90 |
LDFLAGS+=-Wl,-T,$(SRC_PATH)/ppc.ld |
... | ... | |
174 | 179 |
# NOTE: the disassembler code is only needed for debugging |
175 | 180 |
LIBOBJS+=disas.o |
176 | 181 |
ifeq ($(findstring i386, $(TARGET_ARCH) $(ARCH)),i386) |
182 |
USE_I386_DIS=y |
|
183 |
endif |
|
184 |
ifeq ($(findstring amd64, $(TARGET_ARCH) $(ARCH)),amd64) |
|
185 |
USE_I386_DIS=y |
|
186 |
endif |
|
187 |
ifdef USE_I386_DIS |
|
177 | 188 |
LIBOBJS+=i386-dis.o |
178 | 189 |
endif |
179 | 190 |
ifeq ($(findstring alpha, $(TARGET_ARCH) $(ARCH)),alpha) |
b/amd64.ld | ||
---|---|---|
1 |
/* Default linker script, for normal executables */ |
|
2 |
OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") |
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The .ctor section from the crtend file contains the |
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KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) |
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KEEP (*(SORT(.ctors.*))) |
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KEEP (*(.ctors)) |
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{ |
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KEEP (*(SORT(.dtors.*))) |
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KEEP (*(.dtors)) |
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*(.bss .bss.* .gnu.linkonce.b.*) |
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|
131 |
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132 |
. = ALIGN(64 / 8); |
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133 |
} |
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. = ALIGN(64 / 8); |
|
135 |
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PROVIDE (end = .); |
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/* Default linker script, for normal executables */ |
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OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") |
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174 |
OUTPUT_ARCH(i386:x86-64) |
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ENTRY(_start) |
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SEARCH_DIR("/lib64"); SEARCH_DIR("/usr/lib64"); SEARCH_DIR("/usr/local/lib64"); |
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177 |
SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = 0x60000000 + SIZEOF_HEADERS; |
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239 |
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|
240 |
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241 |
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331 |
.debug_abbrev 0 : { *(.debug_abbrev) } |
|
332 |
.debug_line 0 : { *(.debug_line) } |
|
333 |
.debug_frame 0 : { *(.debug_frame) } |
|
334 |
.debug_str 0 : { *(.debug_str) } |
|
335 |
.debug_loc 0 : { *(.debug_loc) } |
|
336 |
.debug_macinfo 0 : { *(.debug_macinfo) } |
|
337 |
/* SGI/MIPS DWARF 2 extensions */ |
|
338 |
.debug_weaknames 0 : { *(.debug_weaknames) } |
|
339 |
.debug_funcnames 0 : { *(.debug_funcnames) } |
|
340 |
.debug_typenames 0 : { *(.debug_typenames) } |
|
341 |
.debug_varnames 0 : { *(.debug_varnames) } |
|
342 |
} |
b/bswap.h | ||
---|---|---|
43 | 43 |
|
44 | 44 |
#endif /* !HAVE_BYTESWAP_H */ |
45 | 45 |
|
46 |
#if defined(__alpha__) || defined (__ia64__) |
|
46 |
#if defined(__alpha__) || defined (__ia64__) || defined(__x86_64__)
|
|
47 | 47 |
#define HOST_LONG_BITS 64 |
48 | 48 |
#else |
49 | 49 |
#define HOST_LONG_BITS 32 |
b/configure | ||
---|---|---|
59 | 59 |
m68k) |
60 | 60 |
cpu="m68k" |
61 | 61 |
;; |
62 |
x86_64|amd64) |
|
63 |
cpu="amd64" |
|
64 |
;; |
|
62 | 65 |
*) |
63 | 66 |
cpu="unknown" |
64 | 67 |
;; |
... | ... | |
253 | 256 |
if test "$cpu" = "i386" ; then |
254 | 257 |
echo "ARCH=i386" >> $config_mak |
255 | 258 |
echo "#define HOST_I386 1" >> $config_h |
259 |
elif test "$cpu" = "amd64" ; then |
|
260 |
echo "ARCH=amd64" >> $config_mak |
|
261 |
echo "#define HOST_AMD64 1" >> $config_h |
|
256 | 262 |
elif test "$cpu" = "armv4l" ; then |
257 | 263 |
echo "ARCH=arm" >> $config_mak |
258 | 264 |
echo "#define HOST_ARM 1" >> $config_h |
b/cpu-exec.c | ||
---|---|---|
785 | 785 |
&uc->uc_sigmask, puc); |
786 | 786 |
} |
787 | 787 |
|
788 |
#elif defined(__x86_64__) |
|
789 |
|
|
790 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
|
791 |
void *puc) |
|
792 |
{ |
|
793 |
struct ucontext *uc = puc; |
|
794 |
unsigned long pc; |
|
795 |
|
|
796 |
pc = uc->uc_mcontext.gregs[REG_RIP]; |
|
797 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
798 |
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
|
799 |
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
|
800 |
&uc->uc_sigmask, puc); |
|
801 |
} |
|
802 |
|
|
788 | 803 |
#elif defined(__powerpc) |
789 | 804 |
|
790 | 805 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
b/dis-asm.h | ||
---|---|---|
16 | 16 |
#define PARAMS(x) x |
17 | 17 |
typedef void *PTR; |
18 | 18 |
typedef uint64_t bfd_vma; |
19 |
typedef int64_t bfd_signed_vma; |
|
19 | 20 |
typedef uint8_t bfd_byte; |
21 |
#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x) |
|
20 | 22 |
|
21 | 23 |
enum bfd_flavour { |
22 | 24 |
bfd_target_unknown_flavour, |
... | ... | |
105 | 107 |
bfd_arch_i386, /* Intel 386 */ |
106 | 108 |
#define bfd_mach_i386_i386 0 |
107 | 109 |
#define bfd_mach_i386_i8086 1 |
110 |
#define bfd_mach_i386_i386_intel_syntax 2 |
|
111 |
#define bfd_mach_x86_64 3 |
|
112 |
#define bfd_mach_x86_64_intel_syntax 4 |
|
108 | 113 |
bfd_arch_we32k, /* AT&T WE32xxx */ |
109 | 114 |
bfd_arch_tahoe, /* CCI/Harris Tahoe */ |
110 | 115 |
bfd_arch_i860, /* Intel 860 */ |
b/disas.c | ||
---|---|---|
140 | 140 |
#else |
141 | 141 |
disasm_info.endian = BFD_ENDIAN_LITTLE; |
142 | 142 |
#endif |
143 |
#ifdef __i386__
|
|
143 |
#if defined(__i386__)
|
|
144 | 144 |
disasm_info.mach = bfd_mach_i386_i386; |
145 | 145 |
print_insn = print_insn_i386; |
146 |
#elif defined(__x86_64__) |
|
147 |
disasm_info.mach = bfd_mach_x86_64; |
|
148 |
print_insn = print_insn_i386; |
|
146 | 149 |
#elif defined(__powerpc__) |
147 | 150 |
print_insn = print_insn_ppc; |
148 | 151 |
#elif defined(__alpha__) |
b/dyngen-exec.h | ||
---|---|---|
68 | 68 |
#define AREG2 "esi" |
69 | 69 |
#define AREG3 "edi" |
70 | 70 |
#endif |
71 |
#ifdef __x86_64__ |
|
72 |
#define AREG0 "rbp" |
|
73 |
#define AREG1 "rbx" |
|
74 |
#define AREG2 "r12" |
|
75 |
#define AREG3 "r13" |
|
76 |
#define AREG4 "r14" |
|
77 |
#define AREG5 "r15" |
|
78 |
#endif |
|
71 | 79 |
#ifdef __powerpc__ |
72 | 80 |
#define AREG0 "r27" |
73 | 81 |
#define AREG1 "r24" |
... | ... | |
188 | 196 |
#ifdef __i386__ |
189 | 197 |
#define EXIT_TB() asm volatile ("ret") |
190 | 198 |
#endif |
199 |
#ifdef __x86_64__ |
|
200 |
#define EXIT_TB() asm volatile ("ret") |
|
201 |
#endif |
|
191 | 202 |
#ifdef __powerpc__ |
192 | 203 |
#define EXIT_TB() asm volatile ("blr") |
193 | 204 |
#endif |
b/dyngen.c | ||
---|---|---|
37 | 37 |
#define elf_check_arch(x) ( ((x) == EM_386) || ((x) == EM_486) ) |
38 | 38 |
#undef ELF_USES_RELOCA |
39 | 39 |
|
40 |
#elif defined(HOST_AMD64) |
|
41 |
|
|
42 |
#define ELF_CLASS ELFCLASS64 |
|
43 |
#define ELF_ARCH EM_X86_64 |
|
44 |
#define elf_check_arch(x) ((x) == EM_X86_64) |
|
45 |
#define ELF_USES_RELOCA |
|
46 |
|
|
40 | 47 |
#elif defined(HOST_PPC) |
41 | 48 |
|
42 | 49 |
#define ELF_CLASS ELFCLASS32 |
... | ... | |
446 | 453 |
start_offset = offset; |
447 | 454 |
switch(ELF_ARCH) { |
448 | 455 |
case EM_386: |
456 |
case EM_X86_64: |
|
449 | 457 |
{ |
450 | 458 |
int len; |
451 | 459 |
len = p_end - p_start; |
... | ... | |
766 | 774 |
} |
767 | 775 |
} |
768 | 776 |
} |
777 |
#elif defined(HOST_AMD64) |
|
778 |
{ |
|
779 |
char name[256]; |
|
780 |
int type; |
|
781 |
int addend; |
|
782 |
for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) { |
|
783 |
if (rel->r_offset >= start_offset && |
|
784 |
rel->r_offset < start_offset + copy_size) { |
|
785 |
sym_name = strtab + symtab[ELFW(R_SYM)(rel->r_info)].st_name; |
|
786 |
if (strstart(sym_name, "__op_param", &p)) { |
|
787 |
snprintf(name, sizeof(name), "param%s", p); |
|
788 |
} else { |
|
789 |
snprintf(name, sizeof(name), "(long)(&%s)", sym_name); |
|
790 |
} |
|
791 |
type = ELF32_R_TYPE(rel->r_info); |
|
792 |
addend = rel->r_addend; |
|
793 |
switch(type) { |
|
794 |
case R_X86_64_32: |
|
795 |
fprintf(outfile, " *(uint32_t *)(gen_code_ptr + %d) = (uint32_t)%s + %d;\n", |
|
796 |
rel->r_offset - start_offset, name, addend); |
|
797 |
break; |
|
798 |
case R_X86_64_32S: |
|
799 |
fprintf(outfile, " *(uint32_t *)(gen_code_ptr + %d) = (int32_t)%s + %d;\n", |
|
800 |
rel->r_offset - start_offset, name, addend); |
|
801 |
break; |
|
802 |
case R_X86_64_PC32: |
|
803 |
fprintf(outfile, " *(uint32_t *)(gen_code_ptr + %d) = %s - (long)(gen_code_ptr + %d) + %d;\n", |
|
804 |
rel->r_offset - start_offset, name, rel->r_offset - start_offset, addend); |
|
805 |
break; |
|
806 |
default: |
|
807 |
error("unsupported AMD64 relocation (%d)", type); |
|
808 |
} |
|
809 |
} |
|
810 |
} |
|
811 |
} |
|
769 | 812 |
#elif defined(HOST_PPC) |
770 | 813 |
{ |
771 | 814 |
char name[256]; |
b/dyngen.h | ||
---|---|---|
27 | 27 |
} |
28 | 28 |
#endif |
29 | 29 |
|
30 |
#ifdef __x86_64__ |
|
31 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
|
32 |
{ |
|
33 |
} |
|
34 |
#endif |
|
35 |
|
|
30 | 36 |
#ifdef __s390__ |
31 | 37 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
32 | 38 |
{ |
b/exec-all.h | ||
---|---|---|
400 | 400 |
} |
401 | 401 |
#endif |
402 | 402 |
|
403 |
#ifdef __x86_64__ |
|
404 |
static inline int testandset (int *p) |
|
405 |
{ |
|
406 |
char ret; |
|
407 |
int readval; |
|
408 |
|
|
409 |
__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0" |
|
410 |
: "=q" (ret), "=m" (*p), "=a" (readval) |
|
411 |
: "r" (1), "m" (*p), "a" (0) |
|
412 |
: "memory"); |
|
413 |
return ret; |
|
414 |
} |
|
415 |
#endif |
|
416 |
|
|
403 | 417 |
#ifdef __s390__ |
404 | 418 |
static inline int testandset (int *p) |
405 | 419 |
{ |
b/i386-dis.c | ||
---|---|---|
1 | 1 |
/* Print i386 instructions for GDB, the GNU debugger. |
2 |
Copyright (C) 1988, 89, 91, 93, 94, 95, 96, 97, 1998 |
|
2 |
Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
|
3 |
2001 |
|
3 | 4 |
Free Software Foundation, Inc. |
4 | 5 |
|
5 | 6 |
This file is part of GDB. |
... | ... | |
22 | 23 |
* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) |
23 | 24 |
* July 1988 |
24 | 25 |
* modified by John Hassey (hassey@dg-rtp.dg.com) |
26 |
* x86-64 support added by Jan Hubicka (jh@suse.cz) |
|
25 | 27 |
*/ |
26 | 28 |
|
27 | 29 |
/* |
... | ... | |
29 | 31 |
* of the "Opcode Map" chapter (Appendix A) of the Intel 80386 |
30 | 32 |
* Programmers Manual. Usually, there is a capital letter, followed |
31 | 33 |
* by a small letter. The capital letter tell the addressing mode, |
32 |
* and the small letter tells about the operand size. Refer to
|
|
34 |
* and the small letter tells about the operand size. Refer to |
|
33 | 35 |
* the Intel manual for details. |
34 | 36 |
*/ |
35 | 37 |
|
36 | 38 |
#include <stdlib.h> |
37 |
#include <setjmp.h> |
|
38 |
|
|
39 | 39 |
#include "dis-asm.h" |
40 | 40 |
|
41 | 41 |
#define MAXLEN 20 |
42 | 42 |
|
43 |
#include <setjmp.h> |
|
44 |
|
|
45 |
#ifndef UNIXWARE_COMPAT |
|
46 |
/* Set non-zero for broken, compatible instructions. Set to zero for |
|
47 |
non-broken opcodes. */ |
|
48 |
#define UNIXWARE_COMPAT 1 |
|
49 |
#endif |
|
50 |
|
|
43 | 51 |
static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); |
52 |
static void ckprefix PARAMS ((void)); |
|
53 |
static const char *prefix_name PARAMS ((int, int)); |
|
54 |
static int print_insn PARAMS ((bfd_vma, disassemble_info *)); |
|
55 |
static void dofloat PARAMS ((int)); |
|
56 |
static void OP_ST PARAMS ((int, int)); |
|
57 |
static void OP_STi PARAMS ((int, int)); |
|
58 |
static int putop PARAMS ((const char *, int)); |
|
59 |
static void oappend PARAMS ((const char *)); |
|
60 |
static void append_seg PARAMS ((void)); |
|
61 |
static void OP_indirE PARAMS ((int, int)); |
|
62 |
static void print_operand_value PARAMS ((char *, int, bfd_vma)); |
|
63 |
static void OP_E PARAMS ((int, int)); |
|
64 |
static void OP_G PARAMS ((int, int)); |
|
65 |
static bfd_vma get64 PARAMS ((void)); |
|
66 |
static bfd_signed_vma get32 PARAMS ((void)); |
|
67 |
static bfd_signed_vma get32s PARAMS ((void)); |
|
68 |
static int get16 PARAMS ((void)); |
|
69 |
static void set_op PARAMS ((bfd_vma, int)); |
|
70 |
static void OP_REG PARAMS ((int, int)); |
|
71 |
static void OP_IMREG PARAMS ((int, int)); |
|
72 |
static void OP_I PARAMS ((int, int)); |
|
73 |
static void OP_I64 PARAMS ((int, int)); |
|
74 |
static void OP_sI PARAMS ((int, int)); |
|
75 |
static void OP_J PARAMS ((int, int)); |
|
76 |
static void OP_SEG PARAMS ((int, int)); |
|
77 |
static void OP_DIR PARAMS ((int, int)); |
|
78 |
static void OP_OFF PARAMS ((int, int)); |
|
79 |
static void OP_OFF64 PARAMS ((int, int)); |
|
80 |
static void ptr_reg PARAMS ((int, int)); |
|
81 |
static void OP_ESreg PARAMS ((int, int)); |
|
82 |
static void OP_DSreg PARAMS ((int, int)); |
|
83 |
static void OP_C PARAMS ((int, int)); |
|
84 |
static void OP_D PARAMS ((int, int)); |
|
85 |
static void OP_T PARAMS ((int, int)); |
|
86 |
static void OP_Rd PARAMS ((int, int)); |
|
87 |
static void OP_MMX PARAMS ((int, int)); |
|
88 |
static void OP_XMM PARAMS ((int, int)); |
|
89 |
static void OP_EM PARAMS ((int, int)); |
|
90 |
static void OP_EX PARAMS ((int, int)); |
|
91 |
static void OP_MS PARAMS ((int, int)); |
|
92 |
static void OP_XS PARAMS ((int, int)); |
|
93 |
static void OP_3DNowSuffix PARAMS ((int, int)); |
|
94 |
static void OP_SIMD_Suffix PARAMS ((int, int)); |
|
95 |
static void SIMD_Fixup PARAMS ((int, int)); |
|
96 |
static void BadOp PARAMS ((void)); |
|
44 | 97 |
|
45 |
struct dis_private |
|
46 |
{ |
|
98 |
struct dis_private { |
|
47 | 99 |
/* Points to first byte not fetched. */ |
48 | 100 |
bfd_byte *max_fetched; |
49 | 101 |
bfd_byte the_buffer[MAXLEN]; |
50 | 102 |
bfd_vma insn_start; |
103 |
int orig_sizeflag; |
|
51 | 104 |
jmp_buf bailout; |
52 | 105 |
}; |
53 | 106 |
|
107 |
/* The opcode for the fwait instruction, which we treat as a prefix |
|
108 |
when we can. */ |
|
109 |
#define FWAIT_OPCODE (0x9b) |
|
110 |
|
|
111 |
/* Set to 1 for 64bit mode disassembly. */ |
|
112 |
static int mode_64bit; |
|
113 |
|
|
114 |
/* Flags for the prefixes for the current instruction. See below. */ |
|
115 |
static int prefixes; |
|
116 |
|
|
117 |
/* REX prefix the current instruction. See below. */ |
|
118 |
static int rex; |
|
119 |
/* Bits of REX we've already used. */ |
|
120 |
static int rex_used; |
|
121 |
#define REX_MODE64 8 |
|
122 |
#define REX_EXTX 4 |
|
123 |
#define REX_EXTY 2 |
|
124 |
#define REX_EXTZ 1 |
|
125 |
/* Mark parts used in the REX prefix. When we are testing for |
|
126 |
empty prefix (for 8bit register REX extension), just mask it |
|
127 |
out. Otherwise test for REX bit is excuse for existence of REX |
|
128 |
only in case value is nonzero. */ |
|
129 |
#define USED_REX(value) \ |
|
130 |
{ \ |
|
131 |
if (value) \ |
|
132 |
rex_used |= (rex & value) ? (value) | 0x40 : 0; \ |
|
133 |
else \ |
|
134 |
rex_used |= 0x40; \ |
|
135 |
} |
|
136 |
|
|
137 |
/* Flags for prefixes which we somehow handled when printing the |
|
138 |
current instruction. */ |
|
139 |
static int used_prefixes; |
|
140 |
|
|
141 |
/* Flags stored in PREFIXES. */ |
|
142 |
#define PREFIX_REPZ 1 |
|
143 |
#define PREFIX_REPNZ 2 |
|
144 |
#define PREFIX_LOCK 4 |
|
145 |
#define PREFIX_CS 8 |
|
146 |
#define PREFIX_SS 0x10 |
|
147 |
#define PREFIX_DS 0x20 |
|
148 |
#define PREFIX_ES 0x40 |
|
149 |
#define PREFIX_FS 0x80 |
|
150 |
#define PREFIX_GS 0x100 |
|
151 |
#define PREFIX_DATA 0x200 |
|
152 |
#define PREFIX_ADDR 0x400 |
|
153 |
#define PREFIX_FWAIT 0x800 |
|
154 |
|
|
54 | 155 |
/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
55 | 156 |
to ADDR (exclusive) are valid. Returns 1 for success, longjmps |
56 | 157 |
on error. */ |
57 | 158 |
#define FETCH_DATA(info, addr) \ |
58 |
((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \ |
|
159 |
((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
|
|
59 | 160 |
? 1 : fetch_data ((info), (addr))) |
60 | 161 |
|
61 | 162 |
static int |
... | ... | |
64 | 165 |
bfd_byte *addr; |
65 | 166 |
{ |
66 | 167 |
int status; |
67 |
struct dis_private *priv = (struct dis_private *)info->private_data; |
|
168 |
struct dis_private *priv = (struct dis_private *) info->private_data;
|
|
68 | 169 |
bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
69 | 170 |
|
70 | 171 |
status = (*info->read_memory_func) (start, |
... | ... | |
73 | 174 |
info); |
74 | 175 |
if (status != 0) |
75 | 176 |
{ |
76 |
(*info->memory_error_func) (status, start, info); |
|
177 |
/* If we did manage to read at least one byte, then |
|
178 |
print_insn_i386 will do something sensible. Otherwise, print |
|
179 |
an error. We do that here because this is where we know |
|
180 |
STATUS. */ |
|
181 |
if (priv->max_fetched == priv->the_buffer) |
|
182 |
(*info->memory_error_func) (status, start, info); |
|
77 | 183 |
longjmp (priv->bailout, 1); |
78 | 184 |
} |
79 | 185 |
else |
... | ... | |
81 | 187 |
return 1; |
82 | 188 |
} |
83 | 189 |
|
190 |
#define XX NULL, 0 |
|
191 |
|
|
84 | 192 |
#define Eb OP_E, b_mode |
85 |
#define indirEb OP_indirE, b_mode |
|
86 |
#define Gb OP_G, b_mode |
|
87 | 193 |
#define Ev OP_E, v_mode |
194 |
#define Ed OP_E, d_mode |
|
195 |
#define indirEb OP_indirE, b_mode |
|
88 | 196 |
#define indirEv OP_indirE, v_mode |
89 | 197 |
#define Ew OP_E, w_mode |
90 | 198 |
#define Ma OP_E, v_mode |
91 |
#define M OP_E, 0 |
|
92 |
#define Mp OP_E, 0 /* ? */ |
|
199 |
#define M OP_E, 0 /* lea, lgdt, etc. */ |
|
200 |
#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ |
|
201 |
#define Gb OP_G, b_mode |
|
93 | 202 |
#define Gv OP_G, v_mode |
203 |
#define Gd OP_G, d_mode |
|
94 | 204 |
#define Gw OP_G, w_mode |
95 |
#define Rw OP_rm, w_mode
|
|
96 |
#define Rd OP_rm, d_mode
|
|
205 |
#define Rd OP_Rd, d_mode
|
|
206 |
#define Rm OP_Rd, m_mode
|
|
97 | 207 |
#define Ib OP_I, b_mode |
98 | 208 |
#define sIb OP_sI, b_mode /* sign extened byte */ |
99 | 209 |
#define Iv OP_I, v_mode |
210 |
#define Iq OP_I, q_mode |
|
211 |
#define Iv64 OP_I64, v_mode |
|
100 | 212 |
#define Iw OP_I, w_mode |
101 | 213 |
#define Jb OP_J, b_mode |
102 | 214 |
#define Jv OP_J, v_mode |
103 |
#if 0 |
|
104 |
#define ONE OP_ONE, 0 |
|
105 |
#endif |
|
106 |
#define Cd OP_C, d_mode |
|
107 |
#define Dd OP_D, d_mode |
|
215 |
#define Cm OP_C, m_mode |
|
216 |
#define Dm OP_D, m_mode |
|
108 | 217 |
#define Td OP_T, d_mode |
109 | 218 |
|
110 |
#define eAX OP_REG, eAX_reg |
|
111 |
#define eBX OP_REG, eBX_reg |
|
112 |
#define eCX OP_REG, eCX_reg |
|
113 |
#define eDX OP_REG, eDX_reg |
|
114 |
#define eSP OP_REG, eSP_reg |
|
115 |
#define eBP OP_REG, eBP_reg |
|
116 |
#define eSI OP_REG, eSI_reg |
|
117 |
#define eDI OP_REG, eDI_reg |
|
118 |
#define AL OP_REG, al_reg |
|
119 |
#define CL OP_REG, cl_reg |
|
120 |
#define DL OP_REG, dl_reg |
|
121 |
#define BL OP_REG, bl_reg |
|
122 |
#define AH OP_REG, ah_reg |
|
123 |
#define CH OP_REG, ch_reg |
|
124 |
#define DH OP_REG, dh_reg |
|
125 |
#define BH OP_REG, bh_reg |
|
126 |
#define AX OP_REG, ax_reg |
|
127 |
#define DX OP_REG, dx_reg |
|
128 |
#define indirDX OP_REG, indir_dx_reg |
|
219 |
#define RMeAX OP_REG, eAX_reg |
|
220 |
#define RMeBX OP_REG, eBX_reg |
|
221 |
#define RMeCX OP_REG, eCX_reg |
|
222 |
#define RMeDX OP_REG, eDX_reg |
|
223 |
#define RMeSP OP_REG, eSP_reg |
|
224 |
#define RMeBP OP_REG, eBP_reg |
|
225 |
#define RMeSI OP_REG, eSI_reg |
|
226 |
#define RMeDI OP_REG, eDI_reg |
|
227 |
#define RMrAX OP_REG, rAX_reg |
|
228 |
#define RMrBX OP_REG, rBX_reg |
|
229 |
#define RMrCX OP_REG, rCX_reg |
|
230 |
#define RMrDX OP_REG, rDX_reg |
|
231 |
#define RMrSP OP_REG, rSP_reg |
|
232 |
#define RMrBP OP_REG, rBP_reg |
|
233 |
#define RMrSI OP_REG, rSI_reg |
|
234 |
#define RMrDI OP_REG, rDI_reg |
|
235 |
#define RMAL OP_REG, al_reg |
|
236 |
#define RMAL OP_REG, al_reg |
|
237 |
#define RMCL OP_REG, cl_reg |
|
238 |
#define RMDL OP_REG, dl_reg |
|
239 |
#define RMBL OP_REG, bl_reg |
|
240 |
#define RMAH OP_REG, ah_reg |
|
241 |
#define RMCH OP_REG, ch_reg |
|
242 |
#define RMDH OP_REG, dh_reg |
|
243 |
#define RMBH OP_REG, bh_reg |
|
244 |
#define RMAX OP_REG, ax_reg |
|
245 |
#define RMDX OP_REG, dx_reg |
|
246 |
|
|
247 |
#define eAX OP_IMREG, eAX_reg |
|
248 |
#define eBX OP_IMREG, eBX_reg |
|
249 |
#define eCX OP_IMREG, eCX_reg |
|
250 |
#define eDX OP_IMREG, eDX_reg |
|
251 |
#define eSP OP_IMREG, eSP_reg |
|
252 |
#define eBP OP_IMREG, eBP_reg |
|
253 |
#define eSI OP_IMREG, eSI_reg |
|
254 |
#define eDI OP_IMREG, eDI_reg |
|
255 |
#define AL OP_IMREG, al_reg |
|
256 |
#define AL OP_IMREG, al_reg |
|
257 |
#define CL OP_IMREG, cl_reg |
|
258 |
#define DL OP_IMREG, dl_reg |
|
259 |
#define BL OP_IMREG, bl_reg |
|
260 |
#define AH OP_IMREG, ah_reg |
|
261 |
#define CH OP_IMREG, ch_reg |
|
262 |
#define DH OP_IMREG, dh_reg |
|
263 |
#define BH OP_IMREG, bh_reg |
|
264 |
#define AX OP_IMREG, ax_reg |
|
265 |
#define DX OP_IMREG, dx_reg |
|
266 |
#define indirDX OP_IMREG, indir_dx_reg |
|
129 | 267 |
|
130 | 268 |
#define Sw OP_SEG, w_mode |
131 |
#define Ap OP_DIR, lptr |
|
132 |
#define Av OP_DIR, v_mode |
|
269 |
#define Ap OP_DIR, 0 |
|
133 | 270 |
#define Ob OP_OFF, b_mode |
271 |
#define Ob64 OP_OFF64, b_mode |
|
134 | 272 |
#define Ov OP_OFF, v_mode |
135 |
#define Xb OP_DSSI, b_mode |
|
136 |
#define Xv OP_DSSI, v_mode |
|
137 |
#define Yb OP_ESDI, b_mode |
|
138 |
#define Yv OP_ESDI, v_mode |
|
273 |
#define Ov64 OP_OFF64, v_mode |
|
274 |
#define Xb OP_DSreg, eSI_reg |
|
275 |
#define Xv OP_DSreg, eSI_reg |
|
276 |
#define Yb OP_ESreg, eDI_reg |
|
277 |
#define Yv OP_ESreg, eDI_reg |
|
278 |
#define DSBX OP_DSreg, eBX_reg |
|
139 | 279 |
|
140 | 280 |
#define es OP_REG, es_reg |
141 | 281 |
#define ss OP_REG, ss_reg |
... | ... | |
145 | 285 |
#define gs OP_REG, gs_reg |
146 | 286 |
|
147 | 287 |
#define MX OP_MMX, 0 |
288 |
#define XM OP_XMM, 0 |
|
148 | 289 |
#define EM OP_EM, v_mode |
149 |
#define MS OP_MS, b_mode |
|
150 |
|
|
151 |
typedef int (*op_rtn) PARAMS ((int bytemode, int aflag, int dflag)); |
|
152 |
|
|
153 |
static int OP_E PARAMS ((int, int, int)); |
|
154 |
static int OP_G PARAMS ((int, int, int)); |
|
155 |
static int OP_I PARAMS ((int, int, int)); |
|
156 |
static int OP_indirE PARAMS ((int, int, int)); |
|
157 |
static int OP_sI PARAMS ((int, int, int)); |
|
158 |
static int OP_REG PARAMS ((int, int, int)); |
|
159 |
static int OP_J PARAMS ((int, int, int)); |
|
160 |
static int OP_DIR PARAMS ((int, int, int)); |
|
161 |
static int OP_OFF PARAMS ((int, int, int)); |
|
162 |
static int OP_ESDI PARAMS ((int, int, int)); |
|
163 |
static int OP_DSSI PARAMS ((int, int, int)); |
|
164 |
static int OP_SEG PARAMS ((int, int, int)); |
|
165 |
static int OP_C PARAMS ((int, int, int)); |
|
166 |
static int OP_D PARAMS ((int, int, int)); |
|
167 |
static int OP_T PARAMS ((int, int, int)); |
|
168 |
static int OP_rm PARAMS ((int, int, int)); |
|
169 |
static int OP_ST PARAMS ((int, int, int)); |
|
170 |
static int OP_STi PARAMS ((int, int, int)); |
|
171 |
#if 0 |
|
172 |
static int OP_ONE PARAMS ((int, int, int)); |
|
173 |
#endif |
|
174 |
static int OP_MMX PARAMS ((int, int, int)); |
|
175 |
static int OP_EM PARAMS ((int, int, int)); |
|
176 |
static int OP_MS PARAMS ((int, int, int)); |
|
177 |
|
|
178 |
static void append_prefix PARAMS ((void)); |
|
179 |
static void set_op PARAMS ((int op)); |
|
180 |
static void putop PARAMS ((char *template, int aflag, int dflag)); |
|
181 |
static void dofloat PARAMS ((int aflag, int dflag)); |
|
182 |
static int get16 PARAMS ((void)); |
|
183 |
static int get32 PARAMS ((void)); |
|
184 |
static void ckprefix PARAMS ((void)); |
|
290 |
#define EX OP_EX, v_mode |
|
291 |
#define MS OP_MS, v_mode |
|
292 |
#define XS OP_XS, v_mode |
|
293 |
#define None OP_E, 0 |
|
294 |
#define OPSUF OP_3DNowSuffix, 0 |
|
295 |
#define OPSIMD OP_SIMD_Suffix, 0 |
|
296 |
|
|
297 |
#define cond_jump_flag NULL, cond_jump_mode |
|
298 |
#define loop_jcxz_flag NULL, loop_jcxz_mode |
|
299 |
|
|
300 |
/* bits in sizeflag */ |
|
301 |
#define SUFFIX_ALWAYS 4 |
|
302 |
#define AFLAG 2 |
|
303 |
#define DFLAG 1 |
|
185 | 304 |
|
186 |
#define b_mode 1 |
|
187 |
#define v_mode 2 |
|
188 |
#define w_mode 3 |
|
189 |
#define d_mode 4 |
|
305 |
#define b_mode 1 /* byte operand */ |
|
306 |
#define v_mode 2 /* operand size depends on prefixes */ |
|
307 |
#define w_mode 3 /* word operand */ |
|
308 |
#define d_mode 4 /* double word operand */ |
|
309 |
#define q_mode 5 /* quad word operand */ |
|
310 |
#define x_mode 6 |
|
311 |
#define m_mode 7 /* d_mode in 32bit, q_mode in 64bit mode. */ |
|
312 |
#define cond_jump_mode 8 |
|
313 |
#define loop_jcxz_mode 9 |
|
190 | 314 |
|
191 | 315 |
#define es_reg 100 |
192 | 316 |
#define cs_reg 101 |
... | ... | |
194 | 318 |
#define ds_reg 103 |
195 | 319 |
#define fs_reg 104 |
196 | 320 |
#define gs_reg 105 |
197 |
#define eAX_reg 107 |
|
198 |
#define eCX_reg 108 |
|
199 |
#define eDX_reg 109 |
|
200 |
#define eBX_reg 110 |
|
201 |
#define eSP_reg 111 |
|
202 |
#define eBP_reg 112 |
|
203 |
#define eSI_reg 113 |
|
204 |
#define eDI_reg 114 |
|
205 | 321 |
|
206 |
#define lptr 115 |
|
322 |
#define eAX_reg 108 |
|
323 |
#define eCX_reg 109 |
|
324 |
#define eDX_reg 110 |
|
325 |
#define eBX_reg 111 |
|
326 |
#define eSP_reg 112 |
|
327 |
#define eBP_reg 113 |
|
328 |
#define eSI_reg 114 |
|
329 |
#define eDI_reg 115 |
|
207 | 330 |
|
208 | 331 |
#define al_reg 116 |
209 | 332 |
#define cl_reg 117 |
... | ... | |
223 | 346 |
#define si_reg 130 |
224 | 347 |
#define di_reg 131 |
225 | 348 |
|
349 |
#define rAX_reg 132 |
|
350 |
#define rCX_reg 133 |
|
351 |
#define rDX_reg 134 |
|
352 |
#define rBX_reg 135 |
|
353 |
#define rSP_reg 136 |
|
354 |
#define rBP_reg 137 |
|
355 |
#define rSI_reg 138 |
|
356 |
#define rDI_reg 139 |
|
357 |
|
|
226 | 358 |
#define indir_dx_reg 150 |
227 | 359 |
|
228 |
#define GRP1b NULL, NULL, 0 |
|
229 |
#define GRP1S NULL, NULL, 1 |
|
230 |
#define GRP1Ss NULL, NULL, 2 |
|
231 |
#define GRP2b NULL, NULL, 3 |
|
232 |
#define GRP2S NULL, NULL, 4 |
|
233 |
#define GRP2b_one NULL, NULL, 5 |
|
234 |
#define GRP2S_one NULL, NULL, 6 |
|
235 |
#define GRP2b_cl NULL, NULL, 7 |
|
236 |
#define GRP2S_cl NULL, NULL, 8 |
|
237 |
#define GRP3b NULL, NULL, 9 |
|
238 |
#define GRP3S NULL, NULL, 10 |
|
239 |
#define GRP4 NULL, NULL, 11 |
|
240 |
#define GRP5 NULL, NULL, 12 |
|
241 |
#define GRP6 NULL, NULL, 13 |
|
242 |
#define GRP7 NULL, NULL, 14 |
|
243 |
#define GRP8 NULL, NULL, 15 |
|
244 |
#define GRP9 NULL, NULL, 16 |
|
245 |
#define GRP10 NULL, NULL, 17 |
|
246 |
#define GRP11 NULL, NULL, 18 |
|
247 |
#define GRP12 NULL, NULL, 19 |
|
248 |
|
|
249 |
#define FLOATCODE 50 |
|
250 |
#define FLOAT NULL, NULL, FLOATCODE |
|
360 |
#define FLOATCODE 1 |
|
361 |
#define USE_GROUPS 2 |
|
362 |
#define USE_PREFIX_USER_TABLE 3 |
|
363 |
#define X86_64_SPECIAL 4 |
|
364 |
|
|
365 |
#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0 |
|
366 |
|
|
367 |
#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0 |
|
368 |
#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0 |
|
369 |
#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0 |
|
370 |
#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0 |
|
371 |
#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0 |
|
372 |
#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0 |
|
373 |
#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0 |
|
374 |
#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0 |
|
375 |
#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0 |
|
376 |
#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0 |
|
377 |
#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0 |
|
378 |
#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0 |
|
379 |
#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0 |
|
380 |
#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0 |
|
381 |
#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0 |
|
382 |
#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0 |
|
383 |
#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0 |
|
384 |
#define GRP10 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0 |
|
385 |
#define GRP11 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0 |
|
386 |
#define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0 |
|
387 |
#define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0 |
|
388 |
#define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0 |
|
389 |
#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0 |
|
390 |
|
|
391 |
#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0 |
|
392 |
#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0 |
|
393 |
#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0 |
|
394 |
#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0 |
|
395 |
#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0 |
|
396 |
#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0 |
|
397 |
#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0 |
|
398 |
#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0 |
|
399 |
#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0 |
|
400 |
#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0 |
|
401 |
#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0 |
|
402 |
#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0 |
|
403 |
#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0 |
|
404 |
#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0 |
|
405 |
#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0 |
|
406 |
#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0 |
|
407 |
#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0 |
|
408 |
#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0 |
|
409 |
#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0 |
|
410 |
#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0 |
|
411 |
#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0 |
|
412 |
#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0 |
|
413 |
#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0 |
|
414 |
#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0 |
|
415 |
#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0 |
|
416 |
#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0 |
|
417 |
#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0 |
|
418 |
|
|
419 |
#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 |
|
420 |
|
|
421 |
typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag)); |
|
251 | 422 |
|
252 | 423 |
struct dis386 { |
253 |
char *name; |
|
424 |
const char *name;
|
|
254 | 425 |
op_rtn op1; |
255 | 426 |
int bytemode1; |
256 | 427 |
op_rtn op2; |
... | ... | |
259 | 430 |
int bytemode3; |
260 | 431 |
}; |
261 | 432 |
|
262 |
static struct dis386 dis386[] = { |
|
433 |
/* Upper case letters in the instruction names here are macros. |
|
434 |
'A' => print 'b' if no register operands or suffix_always is true |
|
435 |
'B' => print 'b' if suffix_always is true |
|
436 |
'E' => print 'e' if 32-bit form of jcxz |
|
437 |
'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
|
438 |
'H' => print ",pt" or ",pn" branch hint |
|
439 |
'L' => print 'l' if suffix_always is true |
|
440 |
'N' => print 'n' if instruction has no wait "prefix" |
|
441 |
'O' => print 'd', or 'o' |
|
442 |
'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
|
443 |
. or suffix_always is true. print 'q' if rex prefix is present. |
|
444 |
'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always |
|
445 |
. is true |
|
446 |
'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode) |
|
447 |
'S' => print 'w', 'l' or 'q' if suffix_always is true |
|
448 |
'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
|
449 |
'U' => print 'q' in 64bit mode and behave as 'Q' otherwise |
|
450 |
'X' => print 's', 'd' depending on data16 prefix (for XMM) |
|
451 |
'W' => print 'b' or 'w' ("w" or "de" in intel mode) |
|
452 |
'Y' => 'q' if instruction has an REX 64bit overwrite prefix |
|
453 |
|
|
454 |
Many of the above letters print nothing in Intel mode. See "putop" |
|
455 |
for the details. |
|
456 |
|
|
457 |
Braces '{' and '}', and vertical bars '|', indicate alternative |
|
458 |
mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel |
|
459 |
modes. In cases where there are only two alternatives, the X86_64 |
|
460 |
instruction is reserved, and "(bad)" is printed. |
|
461 |
*/ |
|
462 |
|
|
463 |
static const struct dis386 dis386[] = { |
|
263 | 464 |
/* 00 */ |
264 |
{ "addb", Eb, Gb },
|
|
265 |
{ "addS", Ev, Gv },
|
|
266 |
{ "addb", Gb, Eb },
|
|
267 |
{ "addS", Gv, Ev },
|
|
268 |
{ "addb", AL, Ib },
|
|
269 |
{ "addS", eAX, Iv },
|
|
270 |
{ "pushS", es },
|
|
271 |
{ "popS", es },
|
|
465 |
{ "addB", Eb, Gb, XX },
|
|
466 |
{ "addS", Ev, Gv, XX },
|
|
467 |
{ "addB", Gb, Eb, XX },
|
|
468 |
{ "addS", Gv, Ev, XX },
|
|
469 |
{ "addB", AL, Ib, XX },
|
|
470 |
{ "addS", eAX, Iv, XX },
|
|
471 |
{ "push{T|}", es, XX, XX },
|
|
472 |
{ "pop{T|}", es, XX, XX },
|
|
272 | 473 |
/* 08 */ |
273 |
{ "orb", Eb, Gb },
|
|
274 |
{ "orS", Ev, Gv },
|
|
275 |
{ "orb", Gb, Eb },
|
|
276 |
{ "orS", Gv, Ev },
|
|
277 |
{ "orb", AL, Ib },
|
|
278 |
{ "orS", eAX, Iv },
|
|
279 |
{ "pushS", cs },
|
|
280 |
{ "(bad)" }, /* 0x0f extended opcode escape */ |
|
474 |
{ "orB", Eb, Gb, XX },
|
|
475 |
{ "orS", Ev, Gv, XX },
|
|
476 |
{ "orB", Gb, Eb, XX },
|
|
477 |
{ "orS", Gv, Ev, XX },
|
|
478 |
{ "orB", AL, Ib, XX },
|
|
479 |
{ "orS", eAX, Iv, XX },
|
|
480 |
{ "push{T|}", cs, XX, XX },
|
|
481 |
{ "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
|
|
281 | 482 |
/* 10 */ |
282 |
{ "adcb", Eb, Gb },
|
|
283 |
{ "adcS", Ev, Gv },
|
|
284 |
{ "adcb", Gb, Eb },
|
|
285 |
{ "adcS", Gv, Ev },
|
|
286 |
{ "adcb", AL, Ib },
|
|
287 |
{ "adcS", eAX, Iv },
|
|
288 |
{ "pushS", ss },
|
|
289 |
{ "popS", ss },
|
|
483 |
{ "adcB", Eb, Gb, XX },
|
|
484 |
{ "adcS", Ev, Gv, XX },
|
|
485 |
{ "adcB", Gb, Eb, XX },
|
|
486 |
{ "adcS", Gv, Ev, XX },
|
|
487 |
{ "adcB", AL, Ib, XX },
|
|
488 |
{ "adcS", eAX, Iv, XX },
|
|
489 |
{ "push{T|}", ss, XX, XX },
|
|
490 |
{ "popT|}", ss, XX, XX },
|
|
290 | 491 |
/* 18 */ |
291 |
{ "sbbb", Eb, Gb },
|
|
292 |
{ "sbbS", Ev, Gv },
|
|
293 |
{ "sbbb", Gb, Eb },
|
|
294 |
{ "sbbS", Gv, Ev },
|
|
295 |
{ "sbbb", AL, Ib },
|
|
296 |
{ "sbbS", eAX, Iv },
|
|
297 |
{ "pushS", ds },
|
|
298 |
{ "popS", ds },
|
|
492 |
{ "sbbB", Eb, Gb, XX },
|
|
493 |
{ "sbbS", Ev, Gv, XX },
|
|
494 |
{ "sbbB", Gb, Eb, XX },
|
|
495 |
{ "sbbS", Gv, Ev, XX },
|
|
496 |
{ "sbbB", AL, Ib, XX },
|
|
497 |
{ "sbbS", eAX, Iv, XX },
|
|
498 |
{ "push{T|}", ds, XX, XX },
|
|
499 |
{ "pop{T|}", ds, XX, XX },
|
|
299 | 500 |
/* 20 */ |
300 |
{ "andb", Eb, Gb },
|
|
301 |
{ "andS", Ev, Gv },
|
|
302 |
{ "andb", Gb, Eb },
|
|
303 |
{ "andS", Gv, Ev },
|
|
304 |
{ "andb", AL, Ib },
|
|
305 |
{ "andS", eAX, Iv },
|
|
306 |
{ "(bad)" }, /* SEG ES prefix */
|
|
307 |
{ "daa" },
|
|
501 |
{ "andB", Eb, Gb, XX },
|
|
502 |
{ "andS", Ev, Gv, XX },
|
|
503 |
{ "andB", Gb, Eb, XX },
|
|
504 |
{ "andS", Gv, Ev, XX },
|
|
505 |
{ "andB", AL, Ib, XX },
|
|
506 |
{ "andS", eAX, Iv, XX },
|
|
507 |
{ "(bad)", XX, XX, XX }, /* SEG ES prefix */
|
|
508 |
{ "daa{|}", XX, XX, XX },
|
|
308 | 509 |
/* 28 */ |
309 |
{ "subb", Eb, Gb },
|
|
310 |
{ "subS", Ev, Gv },
|
|
311 |
{ "subb", Gb, Eb },
|
|
312 |
{ "subS", Gv, Ev },
|
|
313 |
{ "subb", AL, Ib },
|
|
314 |
{ "subS", eAX, Iv },
|
|
315 |
{ "(bad)" }, /* SEG CS prefix */
|
|
316 |
{ "das" },
|
|
510 |
{ "subB", Eb, Gb, XX },
|
|
511 |
{ "subS", Ev, Gv, XX },
|
|
512 |
{ "subB", Gb, Eb, XX },
|
|
513 |
{ "subS", Gv, Ev, XX },
|
|
514 |
{ "subB", AL, Ib, XX },
|
|
515 |
{ "subS", eAX, Iv, XX },
|
|
516 |
{ "(bad)", XX, XX, XX }, /* SEG CS prefix */
|
|
517 |
{ "das{|}", XX, XX, XX },
|
|
317 | 518 |
/* 30 */ |
318 |
{ "xorb", Eb, Gb },
|
|
319 |
{ "xorS", Ev, Gv },
|
|
320 |
{ "xorb", Gb, Eb },
|
|
321 |
{ "xorS", Gv, Ev },
|
|
322 |
{ "xorb", AL, Ib },
|
|
323 |
{ "xorS", eAX, Iv },
|
|
324 |
{ "(bad)" }, /* SEG SS prefix */
|
|
325 |
{ "aaa" },
|
|
519 |
{ "xorB", Eb, Gb, XX },
|
|
520 |
{ "xorS", Ev, Gv, XX },
|
|
521 |
{ "xorB", Gb, Eb, XX },
|
|
522 |
{ "xorS", Gv, Ev, XX },
|
|
523 |
{ "xorB", AL, Ib, XX },
|
|
524 |
{ "xorS", eAX, Iv, XX },
|
|
525 |
{ "(bad)", XX, XX, XX }, /* SEG SS prefix */
|
|
526 |
{ "aaa{|}", XX, XX, XX },
|
|
326 | 527 |
/* 38 */ |
327 |
{ "cmpb", Eb, Gb },
|
|
328 |
{ "cmpS", Ev, Gv },
|
|
329 |
{ "cmpb", Gb, Eb },
|
|
330 |
{ "cmpS", Gv, Ev },
|
|
331 |
{ "cmpb", AL, Ib },
|
|
332 |
{ "cmpS", eAX, Iv },
|
|
333 |
{ "(bad)" }, /* SEG DS prefix */
|
|
334 |
{ "aas" },
|
|
528 |
{ "cmpB", Eb, Gb, XX },
|
|
529 |
{ "cmpS", Ev, Gv, XX },
|
|
530 |
{ "cmpB", Gb, Eb, XX },
|
|
531 |
{ "cmpS", Gv, Ev, XX },
|
|
532 |
{ "cmpB", AL, Ib, XX },
|
|
533 |
{ "cmpS", eAX, Iv, XX },
|
|
534 |
{ "(bad)", XX, XX, XX }, /* SEG DS prefix */
|
|
535 |
{ "aas{|}", XX, XX, XX },
|
|
335 | 536 |
/* 40 */ |
336 |
{ "incS", eAX },
|
|
337 |
{ "incS", eCX },
|
|
338 |
{ "incS", eDX },
|
|
339 |
{ "incS", eBX },
|
|
340 |
{ "incS", eSP },
|
|
341 |
{ "incS", eBP },
|
|
342 |
{ "incS", eSI },
|
|
343 |
{ "incS", eDI },
|
|
537 |
{ "inc{S|}", RMeAX, XX, XX },
|
|
538 |
{ "inc{S|}", RMeCX, XX, XX },
|
|
539 |
{ "inc{S|}", RMeDX, XX, XX },
|
|
540 |
{ "inc{S|}", RMeBX, XX, XX },
|
|
541 |
{ "inc{S|}", RMeSP, XX, XX },
|
|
542 |
{ "inc{S|}", RMeBP, XX, XX },
|
|
543 |
{ "inc{S|}", RMeSI, XX, XX },
|
|
544 |
{ "inc{S|}", RMeDI, XX, XX },
|
|
344 | 545 |
/* 48 */ |
345 |
{ "decS", eAX },
|
|
346 |
{ "decS", eCX },
|
|
347 |
{ "decS", eDX },
|
|
348 |
{ "decS", eBX },
|
|
349 |
{ "decS", eSP },
|
|
350 |
{ "decS", eBP },
|
|
351 |
{ "decS", eSI },
|
|
352 |
{ "decS", eDI },
|
|
546 |
{ "dec{S|}", RMeAX, XX, XX },
|
|
547 |
{ "dec{S|}", RMeCX, XX, XX },
|
|
548 |
{ "dec{S|}", RMeDX, XX, XX },
|
|
549 |
{ "dec{S|}", RMeBX, XX, XX },
|
|
550 |
{ "dec{S|}", RMeSP, XX, XX },
|
|
551 |
{ "dec{S|}", RMeBP, XX, XX },
|
|
552 |
{ "dec{S|}", RMeSI, XX, XX },
|
|
553 |
{ "dec{S|}", RMeDI, XX, XX },
|
|
353 | 554 |
/* 50 */ |
354 |
{ "pushS", eAX },
|
|
355 |
{ "pushS", eCX },
|
|
356 |
{ "pushS", eDX },
|
|
357 |
{ "pushS", eBX },
|
|
358 |
{ "pushS", eSP },
|
|
359 |
{ "pushS", eBP },
|
|
360 |
{ "pushS", eSI },
|
|
361 |
{ "pushS", eDI },
|
|
555 |
{ "pushS", RMrAX, XX, XX },
|
|
556 |
{ "pushS", RMrCX, XX, XX },
|
|
557 |
{ "pushS", RMrDX, XX, XX },
|
|
558 |
{ "pushS", RMrBX, XX, XX },
|
|
559 |
{ "pushS", RMrSP, XX, XX },
|
|
560 |
{ "pushS", RMrBP, XX, XX },
|
|
561 |
{ "pushS", RMrSI, XX, XX },
|
|
562 |
{ "pushS", RMrDI, XX, XX },
|
|
362 | 563 |
/* 58 */ |
363 |
{ "popS", eAX },
|
|
364 |
{ "popS", eCX },
|
|
365 |
{ "popS", eDX },
|
|
366 |
{ "popS", eBX },
|
|
367 |
{ "popS", eSP },
|
|
368 |
{ "popS", eBP },
|
|
369 |
{ "popS", eSI },
|
|
370 |
{ "popS", eDI },
|
|
564 |
{ "popS", RMrAX, XX, XX },
|
|
565 |
{ "popS", RMrCX, XX, XX },
|
|
566 |
{ "popS", RMrDX, XX, XX },
|
|
567 |
{ "popS", RMrBX, XX, XX },
|
|
568 |
{ "popS", RMrSP, XX, XX },
|
|
569 |
{ "popS", RMrBP, XX, XX },
|
|
570 |
{ "popS", RMrSI, XX, XX },
|
|
571 |
{ "popS", RMrDI, XX, XX },
|
|
371 | 572 |
/* 60 */ |
372 |
{ "pusha" },
|
|
373 |
{ "popa" },
|
|
374 |
{ "boundS", Gv, Ma },
|
|
375 |
{ "arpl", Ew, Gw },
|
|
376 |
{ "(bad)" }, /* seg fs */
|
|
377 |
{ "(bad)" }, /* seg gs */
|
|
378 |
{ "(bad)" }, /* op size prefix */
|
|
379 |
{ "(bad)" }, /* adr size prefix */
|
|
573 |
{ "pusha{P|}", XX, XX, XX },
|
|
574 |
{ "popa{P|}", XX, XX, XX },
|
|
575 |
{ "bound{S|}", Gv, Ma, XX },
|
|
576 |
{ X86_64_0 },
|
|
577 |
{ "(bad)", XX, XX, XX }, /* seg fs */
|
|
578 |
{ "(bad)", XX, XX, XX }, /* seg gs */
|
|
579 |
{ "(bad)", XX, XX, XX }, /* op size prefix */
|
|
580 |
{ "(bad)", XX, XX, XX }, /* adr size prefix */
|
|
380 | 581 |
/* 68 */ |
381 |
{ "pushS", Iv }, /* 386 book wrong */
|
|
382 |
{ "imulS", Gv, Ev, Iv }, |
|
383 |
{ "pushS", sIb }, /* push of byte really pushes 2 or 4 bytes */
|
|
384 |
{ "imulS", Gv, Ev, Ib },
|
|
385 |
{ "insb", Yb, indirDX },
|
|
386 |
{ "insS", Yv, indirDX },
|
|
387 |
{ "outsb", indirDX, Xb },
|
|
388 |
{ "outsS", indirDX, Xv },
|
|
582 |
{ "pushT", Iq, XX, XX },
|
|
583 |
{ "imulS", Gv, Ev, Iv },
|
|
584 |
{ "pushT", sIb, XX, XX },
|
|
585 |
{ "imulS", Gv, Ev, sIb },
|
|
586 |
{ "ins{b||b|}", Yb, indirDX, XX },
|
|
587 |
{ "ins{R||R|}", Yv, indirDX, XX },
|
|
588 |
{ "outs{b||b|}", indirDX, Xb, XX },
|
|
589 |
{ "outs{R||R|}", indirDX, Xv, XX },
|
|
389 | 590 |
/* 70 */ |
390 |
{ "jo", Jb },
|
|
391 |
{ "jno", Jb },
|
|
392 |
{ "jb", Jb },
|
|
393 |
{ "jae", Jb },
|
|
394 |
{ "je", Jb },
|
|
395 |
{ "jne", Jb },
|
|
396 |
{ "jbe", Jb },
|
|
397 |
{ "ja", Jb },
|
|
591 |
{ "joH", Jb, XX, cond_jump_flag },
|
|
592 |
{ "jnoH", Jb, XX, cond_jump_flag },
|
|
593 |
{ "jbH", Jb, XX, cond_jump_flag },
|
|
594 |
{ "jaeH", Jb, XX, cond_jump_flag },
|
|
595 |
{ "jeH", Jb, XX, cond_jump_flag },
|
|
596 |
{ "jneH", Jb, XX, cond_jump_flag },
|
|
597 |
{ "jbeH", Jb, XX, cond_jump_flag },
|
|
598 |
{ "jaH", Jb, XX, cond_jump_flag },
|
|
398 | 599 |
/* 78 */ |
399 |
{ "js", Jb },
|
|
400 |
{ "jns", Jb },
|
|
401 |
{ "jp", Jb },
|
|
402 |
{ "jnp", Jb },
|
|
403 |
{ "jl", Jb },
|
|
404 |
{ "jnl", Jb },
|
|
405 |
{ "jle", Jb },
|
|
406 |
{ "jg", Jb },
|
|
600 |
{ "jsH", Jb, XX, cond_jump_flag },
|
|
601 |
{ "jnsH", Jb, XX, cond_jump_flag },
|
|
602 |
{ "jpH", Jb, XX, cond_jump_flag },
|
|
603 |
{ "jnpH", Jb, XX, cond_jump_flag },
|
|
604 |
{ "jlH", Jb, XX, cond_jump_flag },
|
|
605 |
{ "jgeH", Jb, XX, cond_jump_flag },
|
|
606 |
{ "jleH", Jb, XX, cond_jump_flag },
|
|
607 |
{ "jgH", Jb, XX, cond_jump_flag },
|
|
407 | 608 |
/* 80 */ |
408 | 609 |
{ GRP1b }, |
409 | 610 |
{ GRP1S }, |
410 |
{ "(bad)" }, |
|
611 |
{ "(bad)", XX, XX, XX },
|
|
411 | 612 |
{ GRP1Ss }, |
412 |
{ "testb", Eb, Gb },
|
|
413 |
{ "testS", Ev, Gv },
|
|
414 |
{ "xchgb", Eb, Gb },
|
|
415 |
{ "xchgS", Ev, Gv },
|
|
613 |
{ "testB", Eb, Gb, XX },
|
|
614 |
{ "testS", Ev, Gv, XX },
|
|
615 |
{ "xchgB", Eb, Gb, XX },
|
|
616 |
{ "xchgS", Ev, Gv, XX },
|
|
416 | 617 |
/* 88 */ |
417 |
{ "movb", Eb, Gb },
|
|
418 |
{ "movS", Ev, Gv },
|
|
419 |
{ "movb", Gb, Eb },
|
|
420 |
{ "movS", Gv, Ev },
|
|
421 |
{ "movS", Ev, Sw },
|
|
422 |
{ "leaS", Gv, M },
|
|
423 |
{ "movS", Sw, Ev },
|
|
424 |
{ "popS", Ev },
|
|
618 |
{ "movB", Eb, Gb, XX },
|
|
619 |
{ "movS", Ev, Gv, XX },
|
|
620 |
{ "movB", Gb, Eb, XX },
|
|
621 |
{ "movS", Gv, Ev, XX },
|
|
622 |
{ "movQ", Ev, Sw, XX },
|
|
623 |
{ "leaS", Gv, M, XX },
|
|
624 |
{ "movQ", Sw, Ev, XX },
|
|
625 |
{ "popU", Ev, XX, XX },
|
|
425 | 626 |
/* 90 */ |
Also available in: Unified diff