Revision bc687ec9 hw/gt64xxx.c

b/hw/gt64xxx.c
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#ifdef TARGET_WORDS_BIGENDIAN
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    s->regs[GT_CPU]           = 0x00000000;
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#else
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    s->regs[GT_CPU]           = 0x00000800;
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    s->regs[GT_CPU]           = 0x00001000;
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#endif
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    s->regs[GT_MULTI]         = 0x00000000;
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......
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    gt64120_pci_mapping(s);
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}
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static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
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{
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    uint32_t val = pci_default_read_config(d, address, len);
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap32(val);
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#endif
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    return val;
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}
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static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
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                                 int len)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap32(val);
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#endif
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    pci_default_write_config(d, address, val, len);
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}
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PCIBus *pci_gt64120_init(qemu_irq *pic)
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{
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    GT64120State *s;
......
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    cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
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    d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
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                            0, NULL, NULL);
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                            0, gt64120_read_config, gt64120_write_config);
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    d->config[0x00] = 0xab; // vendor_id
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    d->config[0x01] = 0x11;
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    d->config[0x02] = 0x46; // device_id
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    d->config[0x03] = 0x20;
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    d->config[0x02] = 0x20; // device_id
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    d->config[0x03] = 0x46;
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    d->config[0x04] = 0x06;
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    d->config[0x05] = 0x00;
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    d->config[0x06] = 0x80;

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