Revision bcb5fec5 targeti386/op_helper.c
b/targeti386/op_helper.c  

4053  4053  
4054  4054 
void helper_fprem1(void) 
4055  4055 
{ 
4056 
CPU86_LDouble dblq, fpsrcop, fptemp;


4056 
double st0, st1, dblq, fpsrcop, fptemp;


4057  4057 
CPU86_LDoubleU fpsrcop1, fptemp1; 
4058  4058 
int expdif; 
4059  4059 
signed long long int q; 
4060  4060  
4061 
if (isinf(ST0)  isnan(ST0)  isnan(ST1)  (ST1 == 0.0)) { 

4062 
ST0 = 0.0 / 0.0; /* NaN */ 

4061 
st0 = CPU86_LDouble_to_double(ST0); 

4062 
st1 = CPU86_LDouble_to_double(ST1); 

4063  
4064 
if (isinf(st0)  isnan(st0)  isnan(st1)  (st1 == 0.0)) { 

4065 
ST0 = double_to_CPU86_LDouble(0.0 / 0.0); /* NaN */ 

4063  4066 
env>fpus &= (~0x4700); /* (C3,C2,C1,C0) < 0000 */ 
4064  4067 
return; 
4065  4068 
} 
4066  4069  
4067 
fpsrcop = ST0;


4068 
fptemp = ST1;


4069 
fpsrcop1.d = fpsrcop;


4070 
fptemp1.d = fptemp;


4070 
fpsrcop = st0;


4071 
fptemp = st1;


4072 
fpsrcop1.d = ST0;


4073 
fptemp1.d = ST1;


4071  4074 
expdif = EXPD(fpsrcop1)  EXPD(fptemp1); 
4072  4075  
4073  4076 
if (expdif < 0) { 
...  ...  
4081  4084 
dblq = fpsrcop / fptemp; 
4082  4085 
/* round dblq towards nearest integer */ 
4083  4086 
dblq = rint(dblq); 
4084 
ST0 = fpsrcop  fptemp * dblq;


4087 
st0 = fpsrcop  fptemp * dblq;


4085  4088  
4086  4089 
/* convert dblq to q by truncating towards zero */ 
4087  4090 
if (dblq < 0.0) 
...  ...  
4097  4100 
} else { 
4098  4101 
env>fpus = 0x400; /* C2 < 1 */ 
4099  4102 
fptemp = pow(2.0, expdif  50); 
4100 
fpsrcop = (ST0 / ST1) / fptemp;


4103 
fpsrcop = (st0 / st1) / fptemp;


4101  4104 
/* fpsrcop = integer obtained by chopping */ 
4102  4105 
fpsrcop = (fpsrcop < 0.0) ? 
4103  4106 
(floor(fabs(fpsrcop))) : floor(fpsrcop); 
4104 
ST0 = (ST1 * fpsrcop * fptemp);


4107 
st0 = (st1 * fpsrcop * fptemp);


4105  4108 
} 
4109 
ST0 = double_to_CPU86_LDouble(st0); 

4106  4110 
} 
4107  4111  
4108  4112 
void helper_fprem(void) 
4109  4113 
{ 
4110 
CPU86_LDouble dblq, fpsrcop, fptemp;


4114 
double st0, st1, dblq, fpsrcop, fptemp;


4111  4115 
CPU86_LDoubleU fpsrcop1, fptemp1; 
4112  4116 
int expdif; 
4113  4117 
signed long long int q; 
4114  4118  
4115 
if (isinf(ST0)  isnan(ST0)  isnan(ST1)  (ST1 == 0.0)) { 

4116 
ST0 = 0.0 / 0.0; /* NaN */ 

4119 
st0 = CPU86_LDouble_to_double(ST0); 

4120 
st1 = CPU86_LDouble_to_double(ST1); 

4121  
4122 
if (isinf(st0)  isnan(st0)  isnan(st1)  (st1 == 0.0)) { 

4123 
ST0 = double_to_CPU86_LDouble(0.0 / 0.0); /* NaN */ 

4117  4124 
env>fpus &= (~0x4700); /* (C3,C2,C1,C0) < 0000 */ 
4118  4125 
return; 
4119  4126 
} 
4120  4127  
4121 
fpsrcop = (CPU86_LDouble)ST0;


4122 
fptemp = (CPU86_LDouble)ST1;


4123 
fpsrcop1.d = fpsrcop;


4124 
fptemp1.d = fptemp;


4128 
fpsrcop = st0;


4129 
fptemp = st1;


4130 
fpsrcop1.d = ST0;


4131 
fptemp1.d = ST1;


4125  4132 
expdif = EXPD(fpsrcop1)  EXPD(fptemp1); 
4126  4133  
4127  4134 
if (expdif < 0) { 
...  ...  
4135  4142 
dblq = fpsrcop/*ST0*/ / fptemp/*ST1*/; 
4136  4143 
/* round dblq towards zero */ 
4137  4144 
dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq); 
4138 
ST0 = fpsrcop/*ST0*/  fptemp * dblq;


4145 
st0 = fpsrcop/*ST0*/  fptemp * dblq;


4139  4146  
4140  4147 
/* convert dblq to q by truncating towards zero */ 
4141  4148 
if (dblq < 0.0) 
...  ...  
4152  4159 
int N = 32 + (expdif % 32); /* as per AMD docs */ 
4153  4160 
env>fpus = 0x400; /* C2 < 1 */ 
4154  4161 
fptemp = pow(2.0, (double)(expdif  N)); 
4155 
fpsrcop = (ST0 / ST1) / fptemp;


4162 
fpsrcop = (st0 / st1) / fptemp;


4156  4163 
/* fpsrcop = integer obtained by chopping */ 
4157  4164 
fpsrcop = (fpsrcop < 0.0) ? 
4158  4165 
(floor(fabs(fpsrcop))) : floor(fpsrcop); 
4159 
ST0 = (ST1 * fpsrcop * fptemp);


4166 
st0 = (st1 * fpsrcop * fptemp);


4160  4167 
} 
4168 
ST0 = double_to_CPU86_LDouble(st0); 

4161  4169 
} 
4162  4170  
4163  4171 
void helper_fyl2xp1(void) 
Also available in: Unified diff