Revision bd4b65ee hw/pci.h
| b/hw/pci.h | ||
|---|---|---|
| 101 | 101 |
#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ |
| 102 | 102 |
#define PCI_STATUS 0x06 /* 16 bits */ |
| 103 | 103 |
#define PCI_REVISION_ID 0x08 /* 8 bits */ |
| 104 |
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
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| 104 | 105 |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| 105 | 106 |
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
| 106 | 107 |
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
| ... | ... | |
| 159 | 160 |
/* PCI config space */ |
| 160 | 161 |
uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
| 161 | 162 |
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| 163 |
/* Used to enable config checks on load. Note that writeable bits are |
|
| 164 |
* never checked even if set in cmask. */ |
|
| 165 |
uint8_t cmask[PCI_CONFIG_SPACE_SIZE]; |
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| 166 |
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| 162 | 167 |
/* Used to implement R/W bytes */ |
| 163 | 168 |
uint8_t wmask[PCI_CONFIG_SPACE_SIZE]; |
| 164 | 169 |
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