Revision bd7d9a6d
| b/target-ppc/cpu.h | ||
|---|---|---|
| 27 | 27 |
|
| 28 | 28 |
#if defined (TARGET_PPC64) |
| 29 | 29 |
/* PowerPC 64 definitions */ |
| 30 |
typedef uint64_t ppc_gpr_t; |
|
| 31 | 30 |
#define TARGET_LONG_BITS 64 |
| 32 | 31 |
#define TARGET_PAGE_BITS 12 |
| 33 | 32 |
|
| 34 | 33 |
#else /* defined (TARGET_PPC64) */ |
| 35 | 34 |
/* PowerPC 32 definitions */ |
| 36 |
typedef uint32_t ppc_gpr_t; |
|
| 37 | 35 |
#define TARGET_LONG_BITS 32 |
| 38 | 36 |
|
| 39 | 37 |
#if defined(TARGET_PPCEMB) |
| ... | ... | |
| 531 | 529 |
/* First are the most commonly used resources |
| 532 | 530 |
* during translated code execution |
| 533 | 531 |
*/ |
| 534 |
#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64) |
|
| 532 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
| 533 |
target_ulong t0, t1, t2; |
|
| 534 |
#endif |
|
| 535 |
#if !defined(TARGET_PPC64) |
|
| 535 | 536 |
/* temporary fixed-point registers |
| 536 |
* used to emulate 64 bits registers on 32 bits hosts
|
|
| 537 |
* used to emulate 64 bits registers on 32 bits targets
|
|
| 537 | 538 |
*/ |
| 538 |
uint64_t t0, t1, t2;
|
|
| 539 |
uint64_t t0_64, t1_64, t2_64;
|
|
| 539 | 540 |
#endif |
| 540 | 541 |
ppc_avr_t avr0, avr1, avr2; |
| 541 | 542 |
|
| 542 | 543 |
/* general purpose registers */ |
| 543 |
ppc_gpr_t gpr[32];
|
|
| 544 |
target_ulong gpr[32];
|
|
| 544 | 545 |
#if !defined(TARGET_PPC64) |
| 545 | 546 |
/* Storage for GPR MSB, used by the SPE extension */ |
| 546 |
ppc_gpr_t gprh[32];
|
|
| 547 |
target_ulong gprh[32];
|
|
| 547 | 548 |
#endif |
| 548 | 549 |
/* LR */ |
| 549 | 550 |
target_ulong lr; |
| ... | ... | |
| 561 | 562 |
/* machine state register */ |
| 562 | 563 |
target_ulong msr; |
| 563 | 564 |
/* temporary general purpose registers */ |
| 564 |
ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
|
|
| 565 |
target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
|
|
| 565 | 566 |
|
| 566 | 567 |
/* Floating point execution context */ |
| 567 | 568 |
/* temporary float registers */ |
| ... | ... | |
| 614 | 615 |
ppc_avr_t avr[32]; |
| 615 | 616 |
uint32_t vscr; |
| 616 | 617 |
/* SPE registers */ |
| 617 |
ppc_gpr_t spe_acc;
|
|
| 618 |
target_ulong spe_acc;
|
|
| 618 | 619 |
float_status spe_status; |
| 619 | 620 |
uint32_t spe_fscr; |
| 620 | 621 |
|
| b/target-ppc/exec.h | ||
|---|---|---|
| 39 | 39 |
#define T2 (env->t2) |
| 40 | 40 |
#define TDX "%016" PRIx64 |
| 41 | 41 |
#else |
| 42 |
register unsigned long T0 asm(AREG1);
|
|
| 43 |
register unsigned long T1 asm(AREG2);
|
|
| 44 |
register unsigned long T2 asm(AREG3);
|
|
| 42 |
register target_ulong T0 asm(AREG1);
|
|
| 43 |
register target_ulong T1 asm(AREG2);
|
|
| 44 |
register target_ulong T2 asm(AREG3);
|
|
| 45 | 45 |
#define TDX "%016lx" |
| 46 | 46 |
#endif |
| 47 | 47 |
/* We may, sometime, need 64 bits registers on 32 bits targets */ |
| 48 |
#if (HOST_LONG_BITS == 32) |
|
| 49 |
/* no registers can be used */ |
|
| 50 |
#define T0_64 (env->t0) |
|
| 51 |
#define T1_64 (env->t1) |
|
| 52 |
#define T2_64 (env->t2) |
|
| 48 |
#if !defined(TARGET_PPC64) |
|
| 49 |
#define T0_64 (env->t0_64) |
|
| 50 |
#define T1_64 (env->t1_64) |
|
| 51 |
#define T2_64 (env->t2_64) |
|
| 53 | 52 |
#else |
| 54 | 53 |
#define T0_64 T0 |
| 55 | 54 |
#define T1_64 T1 |
| b/target-ppc/helper_regs.h | ||
|---|---|---|
| 42 | 42 |
/* Swap temporary saved registers with GPRs */ |
| 43 | 43 |
static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env) |
| 44 | 44 |
{
|
| 45 |
ppc_gpr_t tmp;
|
|
| 45 |
target_ulong tmp;
|
|
| 46 | 46 |
|
| 47 | 47 |
tmp = env->gpr[0]; |
| 48 | 48 |
env->gpr[0] = env->tgpr[0]; |
| b/target-ppc/translate.c | ||
|---|---|---|
| 90 | 90 |
#endif |
| 91 | 91 |
#if !defined(TARGET_PPC64) |
| 92 | 92 |
cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64, |
| 93 |
TCG_AREG0, offsetof(CPUState, t0), |
|
| 93 |
TCG_AREG0, offsetof(CPUState, t0_64),
|
|
| 94 | 94 |
"T0_64"); |
| 95 | 95 |
cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64, |
| 96 |
TCG_AREG0, offsetof(CPUState, t1), |
|
| 96 |
TCG_AREG0, offsetof(CPUState, t1_64),
|
|
| 97 | 97 |
"T1_64"); |
| 98 | 98 |
cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64, |
| 99 |
TCG_AREG0, offsetof(CPUState, t2), |
|
| 99 |
TCG_AREG0, offsetof(CPUState, t2_64),
|
|
| 100 | 100 |
"T2_64"); |
| 101 | 101 |
#endif |
| 102 | 102 |
|
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