Archipelago » qemu

            if (s->fifo_len == 0)

                s->sr &= ~MCF_UART_RxRDY;

            mcf_uart_update(s);

            return val;

        }

    case 0x10:

        if (s->read_count == s->read_trigger - 1)

            s->int_level &= ~ PL011_INT_RX;

        pl011_update(s);

        return c;

    case 1: /* UARTCR */

        return 0;

            ret = s->rbr;

            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);

            serial_update_irq(s);

        }

        break;

    case 1:

        else

            ret = s->rx;

        SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);

        return ret;

    default:

        break;

    void *handler_opaque;

    void (*chr_send_event)(struct CharDriverState *chr, int event);

    void (*chr_close)(struct CharDriverState *chr);

    void *opaque;

    int focus;

    QEMUBH *bh;

void qemu_chr_reset(CharDriverState *s);

int qemu_chr_can_read(CharDriverState *s);

void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);

/* async I/O support */

    s->chr_read(s->handler_opaque, buf, len);

}

void qemu_chr_printf(CharDriverState *s, const char *fmt, ...)

{

static int term_timestamps;

static int64_t term_timestamps_start;

#define MAX_MUX 4

typedef struct {

    IOCanRWHandler *chr_can_read[MAX_MUX];

    IOReadHandler *chr_read[MAX_MUX];

    IOEventHandler *chr_event[MAX_MUX];

    void *ext_opaque[MAX_MUX];

    CharDriverState *drv;

    int mux_cnt;

    int term_got_escape;

    int max_size;

    return 0;

}

static int mux_chr_can_read(void *opaque)

{

    CharDriverState *chr = opaque;

    MuxDriver *d = chr->opaque;

    if (d->chr_can_read[chr->focus])

    return 0;

}

{

    CharDriverState *chr = opaque;

    MuxDriver *d = chr->opaque;

    int i;

    for(i = 0; i < size; i++)

}

static void mux_chr_event(void *opaque, int event)

    chr->focus = -1;

    chr->chr_write = mux_chr_write;

    chr->chr_update_read_handler = mux_chr_update_read_handler;

    return chr;

}