Revision be210acb
b/tcg/README | ||
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282 | 282 |
Indicate that the value of t0 won't be used later. It is useful to |
283 | 283 |
force dead code elimination. |
284 | 284 |
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********* Conditional moves |
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* setcond_i32/i64 cond, dest, t1, t2 |
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dest = (t1 cond t2) |
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Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0. |
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285 | 293 |
********* Type conversions |
286 | 294 |
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287 | 295 |
* ext_i32_i64 t0, t1 |
... | ... | |
346 | 354 |
Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding |
347 | 355 |
the full 64-bit product T0. The later is returned in two 32-bit outputs. |
348 | 356 |
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357 |
* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high |
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358 |
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Similar to setcond, except that the 64-bit values T1 and T2 are |
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formed from two 32-bit arguments. The result is a 32-bit value. |
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349 | 362 |
********* QEMU specific operations |
350 | 363 |
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351 | 364 |
* tb_exit t0 |
b/tcg/tcg-op.h | ||
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280 | 280 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
281 | 281 |
} |
282 | 282 |
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283 |
static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, |
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TCGv_i32 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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293 |
*gen_opparam_ptr++ = arg6; |
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} |
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295 |
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296 |
static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, |
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TCGv_i64 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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283 | 309 |
static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
284 | 310 |
TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, |
285 | 311 |
TCGArg arg6) |
... | ... | |
1795 | 1821 |
} |
1796 | 1822 |
} |
1797 | 1823 |
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1824 |
static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, |
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1825 |
TCGv_i32 arg1, TCGv_i32 arg2) |
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{ |
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1827 |
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
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1828 |
} |
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1829 |
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1830 |
static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
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TCGv_i64 arg1, TCGv_i64 arg2) |
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{ |
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#if TCG_TARGET_REG_BITS == 64 |
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tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
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1835 |
#else |
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1836 |
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
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TCGV_LOW(arg1), TCGV_HIGH(arg1), |
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TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
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tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
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#endif |
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} |
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/***************************************/ |
1799 | 1844 |
/* QEMU specific operations. Their type depend on the QEMU CPU |
1800 | 1845 |
type. */ |
... | ... | |
2067 | 2112 |
#define tcg_gen_sari_tl tcg_gen_sari_i64 |
2068 | 2113 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
2069 | 2114 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
2115 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
|
2070 | 2116 |
#define tcg_gen_mul_tl tcg_gen_mul_i64 |
2071 | 2117 |
#define tcg_gen_muli_tl tcg_gen_muli_i64 |
2072 | 2118 |
#define tcg_gen_div_tl tcg_gen_div_i64 |
... | ... | |
2137 | 2183 |
#define tcg_gen_sari_tl tcg_gen_sari_i32 |
2138 | 2184 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
2139 | 2185 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
2186 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
|
2140 | 2187 |
#define tcg_gen_mul_tl tcg_gen_mul_i32 |
2141 | 2188 |
#define tcg_gen_muli_tl tcg_gen_muli_i32 |
2142 | 2189 |
#define tcg_gen_div_tl tcg_gen_div_i32 |
b/tcg/tcg-opc.h | ||
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42 | 42 |
|
43 | 43 |
DEF2(mov_i32, 1, 1, 0, 0) |
44 | 44 |
DEF2(movi_i32, 1, 0, 1, 0) |
45 |
DEF2(setcond_i32, 1, 2, 1, 0) |
|
45 | 46 |
/* load/store */ |
46 | 47 |
DEF2(ld8u_i32, 1, 1, 1, 0) |
47 | 48 |
DEF2(ld8s_i32, 1, 1, 1, 0) |
... | ... | |
82 | 83 |
DEF2(sub2_i32, 2, 4, 0, 0) |
83 | 84 |
DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
84 | 85 |
DEF2(mulu2_i32, 2, 2, 0, 0) |
86 |
DEF2(setcond2_i32, 1, 4, 1, 0) |
|
85 | 87 |
#endif |
86 | 88 |
#ifdef TCG_TARGET_HAS_ext8s_i32 |
87 | 89 |
DEF2(ext8s_i32, 1, 1, 0, 0) |
... | ... | |
111 | 113 |
#if TCG_TARGET_REG_BITS == 64 |
112 | 114 |
DEF2(mov_i64, 1, 1, 0, 0) |
113 | 115 |
DEF2(movi_i64, 1, 0, 1, 0) |
116 |
DEF2(setcond_i64, 1, 2, 1, 0) |
|
114 | 117 |
/* load/store */ |
115 | 118 |
DEF2(ld8u_i64, 1, 1, 1, 0) |
116 | 119 |
DEF2(ld8s_i64, 1, 1, 1, 0) |
b/tcg/tcg.c | ||
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670 | 670 |
} |
671 | 671 |
#endif |
672 | 672 |
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673 |
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673 | 674 |
static void tcg_reg_alloc_start(TCGContext *s) |
674 | 675 |
{ |
675 | 676 |
int i; |
... | ... | |
888 | 889 |
fprintf(outfile, "%s", |
889 | 890 |
tcg_get_arg_str_idx(s, buf, sizeof(buf), args[k++])); |
890 | 891 |
} |
891 |
if (c == INDEX_op_brcond_i32 |
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switch (c) { |
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893 |
case INDEX_op_brcond_i32: |
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894 |
#if TCG_TARGET_REG_BITS == 32 |
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895 |
case INDEX_op_brcond2_i32: |
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#elif TCG_TARGET_REG_BITS == 64 |
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case INDEX_op_brcond_i64: |
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#endif |
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case INDEX_op_setcond_i32: |
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892 | 900 |
#if TCG_TARGET_REG_BITS == 32 |
893 |
|| c == INDEX_op_brcond2_i32
|
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case INDEX_op_setcond2_i32:
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894 | 902 |
#elif TCG_TARGET_REG_BITS == 64 |
895 |
|| c == INDEX_op_brcond_i64
|
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903 |
case INDEX_op_setcond_i64:
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896 | 904 |
#endif |
897 |
) { |
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898 | 905 |
if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) |
899 | 906 |
fprintf(outfile, ",%s", cond_name[args[k++]]); |
900 | 907 |
else |
901 | 908 |
fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]); |
902 | 909 |
i = 1; |
903 |
}
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904 |
else
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break;
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911 |
default:
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905 | 912 |
i = 0; |
913 |
break; |
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914 |
} |
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906 | 915 |
for(; i < nb_cargs; i++) { |
907 | 916 |
if (k != 0) |
908 | 917 |
fprintf(outfile, ","); |
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