Revision bee8d684 hw/cirrus_vga.c

b/hw/cirrus_vga.c
2985 2985
    qemu_put_buffer(f, s->gr + 2, 254);
2986 2986
    qemu_put_8s(f, &s->ar_index);
2987 2987
    qemu_put_buffer(f, s->ar, 21);
2988
    qemu_put_be32s(f, &s->ar_flip_flop);
2988
    qemu_put_be32(f, s->ar_flip_flop);
2989 2989
    qemu_put_8s(f, &s->cr_index);
2990 2990
    qemu_put_buffer(f, s->cr, 256);
2991 2991
    qemu_put_8s(f, &s->msr);
......
3000 3000
    qemu_put_buffer(f, s->dac_cache, 3);
3001 3001
    qemu_put_buffer(f, s->palette, 768);
3002 3002

  
3003
    qemu_put_be32s(f, &s->bank_offset);
3003
    qemu_put_be32(f, s->bank_offset);
3004 3004

  
3005 3005
    qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3006 3006
    qemu_put_8s(f, &s->cirrus_hidden_dac_data);
......
3036 3036
    qemu_get_buffer(f, s->gr + 2, 254);
3037 3037
    qemu_get_8s(f, &s->ar_index);
3038 3038
    qemu_get_buffer(f, s->ar, 21);
3039
    qemu_get_be32s(f, &s->ar_flip_flop);
3039
    s->ar_flip_flop=qemu_get_be32(f);
3040 3040
    qemu_get_8s(f, &s->cr_index);
3041 3041
    qemu_get_buffer(f, s->cr, 256);
3042 3042
    qemu_get_8s(f, &s->msr);
......
3051 3051
    qemu_get_buffer(f, s->dac_cache, 3);
3052 3052
    qemu_get_buffer(f, s->palette, 768);
3053 3053

  
3054
    qemu_get_be32s(f, &s->bank_offset);
3054
    s->bank_offset=qemu_get_be32(f);
3055 3055

  
3056 3056
    qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3057 3057
    qemu_get_8s(f, &s->cirrus_hidden_dac_data);

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