Archipelago » qemu

                    next_tb = tcg_qemu_tb_exec(tc_ptr);

                    env->current_tb = NULL;

                    if ((next_tb & 3) == 2) {

                        int insns_left;

                        tb = (TranslationBlock *)(long)(next_tb & ~3);

                        /* Restore PC.  */

    return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;

}

   instruction of a TB so that interrupts take effect immediately.  */

static inline int can_do_io(CPUState *env)

{

   cpu_exec() */

CPUState *cpu_single_env;

/* 0 = Do not count executed instructions.

   2 = Adaptive rate instruction counting.  */

int use_icount = 0;

/* Current instruction counter.  While executing translated code this may

void tb_free(TranslationBlock *tb)

{

       Ignore the hard cases and just back up if this TB happens to

       be the last one generated.  */

    if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {

    old_mask = env->interrupt_request;

    /* FIXME: This is probably not threadsafe.  A different thread could

    env->interrupt_request |= mask;

#if defined(USE_NPTL)

    /* FIXME: TB unchaining isn't SMP safe.  For now just ignore the

    n = env->icount_decr.u16.low + tb->icount;

    cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);

    /* Calculate how many instructions had been executed before the fault

    n = n - env->icount_decr.u16.low;

    /* Generate a new TB ending on the I/O insn.  */

    n++;

    /* On MIPS and SH, delay slot instructions can only be restarted if

       they were already the first instruction in the TB.  If this is not

       branch.  */

#if defined(TARGET_MIPS)

    if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {

    /* FIXME: In theory this could raise an exception.  In practice

       we have already translated the block once so it's probably ok.  */

    tb_gen_code(env, pc, cs_base, flags, cflags);

       the first in the TB) then we end up generating a whole new TB and

       repeating the fault, which is horribly inefficient.

       Better would be to execute just this insn uncached, or generate a

static TCGArg *icount_arg;

static int icount_label;

        /* Translation stops when a conditional branch is enoutered.

         * Otherwise the subsequent code could get translated several times.

         * Also stop translation when a page boundary is reached.  This

        num_insns ++;

    } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&

             !env->singlestep_enabled &&

                num_insns++;

		/* Check for delayed branches here. If we do it before

		   loop doing nothing for on this program location.  */

		if (dc->delayed_branch) {

			dc->delayed_branch--;

        num_insns++;

        /* Terminate the TB on memory ops if watchpoints are present.  */

         * IRQ raising bits.  */

        if (dc->is_mem && env->nb_watchpoints)

            break;

                rn, reg, sel);

    }

#endif

    if (use_icount) {

        gen_io_end();

        ctx->bstate = BS_STOP;

    }

#endif

    tcg_temp_free(t0);

    if (use_icount) {

        gen_io_end();

        ctx->bstate = BS_STOP;

static CPUState *cur_cpu;

static CPUState *next_cpu;

static int event_pending = 1;

static int icount_time_shift;

#define MAX_ICOUNT_SHIFT 10

/* Compensate for varying guest execution speed.  */

static int64_t qemu_icount_bias;

#endif /* _WIN32 */

/* Correlation between real and virtual time is always going to be

   When the guest is idle real and virtual time will be aligned in

   the IO wait loop.  */

#define ICOUNT_WOBBLE (QEMU_TIMER_BASE / 10)

                    if (use_icount == 1) {

                        /* When not using an adaptive execution frequency

                           we tend to get badly out of sync with real time,

                        delta = 0;

                    } else {

                        delta = cpu_get_icount() - cpu_get_clock();