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/*
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* QEMU ETRAX Ethernet Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include "hw.h" |
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#include "net.h" |
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#include "etraxfs_dma.h" |
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#define D(x)
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/* Advertisement control register. */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
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|
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/*
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* The MDIO extensions in the TDK PHY model were reversed engineered from the
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* linux driver (PHYID and Diagnostics reg).
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* TODO: Add friendly names for the register nums.
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*/
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struct qemu_phy
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{
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uint32_t regs[32];
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|
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unsigned int (*read)(struct qemu_phy *phy, unsigned int req); |
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void (*write)(struct qemu_phy *phy, unsigned int req, |
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unsigned int data); |
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}; |
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|
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static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) |
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{
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int regnum;
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unsigned r = 0; |
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regnum = req & 0x1f;
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switch (regnum) {
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case 1: |
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14); |
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r |= (1 << 11) | (1 << 12); |
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r |= (1 << 5); /* Autoneg complete. */ |
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r |= (1 << 3); /* Autoneg able. */ |
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r |= (1 << 2); /* Link. */ |
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break;
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case 5: |
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */ |
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5); |
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/* Autoneg support. */
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r |= 1;
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break;
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case 18: |
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{
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/* Diagnostics reg. */
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int duplex = 0; |
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int speed_100 = 0; |
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11); |
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} |
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break;
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default:
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r = phy->regs[regnum]; |
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break;
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} |
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D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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} |
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static void |
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tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) |
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{
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int regnum;
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regnum = req & 0x1f;
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D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data; |
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break;
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} |
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} |
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static void |
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tdk_init(struct qemu_phy *phy)
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{
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phy->regs[0] = 0x3100; |
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/* PHY Id. */
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phy->regs[2] = 0x0300; |
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phy->regs[3] = 0xe400; |
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1; |
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phy->read = tdk_read; |
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phy->write = tdk_write; |
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} |
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struct qemu_mdio
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{
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE, |
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SOF, |
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OPC, |
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ADDR, |
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REQ, |
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TURNAROUND, |
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DATA |
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} state; |
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unsigned int drive; |
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|
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unsigned int cnt; |
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unsigned int addr; |
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unsigned int opc; |
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unsigned int req; |
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unsigned int data; |
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struct qemu_phy *devs[32]; |
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}; |
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static void |
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mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
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{
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bus->devs[addr & 0x1f] = phy;
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void |
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mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
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{
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bus->devs[addr & 0x1f] = NULL; |
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} |
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#endif
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static void mdio_read_req(struct qemu_mdio *bus) |
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{
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr]; |
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if (phy && phy->read)
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bus->data = phy->read(phy, bus->req); |
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else
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bus->data = 0xffff;
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} |
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static void mdio_write_req(struct qemu_mdio *bus) |
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{
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr]; |
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if (phy && phy->write)
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phy->write(phy, bus->req, bus->data); |
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} |
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|
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static void mdio_cycle(struct qemu_mdio *bus) |
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{
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bus->cnt++; |
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D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
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bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); |
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#if 0
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if (bus->mdc)
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printf("%d", bus->mdio);
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#endif
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switch (bus->state)
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{
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case PREAMBLE:
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if (bus->mdc) {
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if (bus->cnt >= (32 * 2) && !bus->mdio) { |
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bus->cnt = 0;
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bus->state = SOF; |
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bus->data = 0;
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} |
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} |
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break;
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case SOF:
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if (bus->mdc) {
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if (bus->mdio != 1) |
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printf("WARNING: no SOF\n");
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if (bus->cnt == 1*2) { |
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bus->cnt = 0;
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bus->opc = 0;
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bus->state = OPC; |
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} |
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} |
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break;
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case OPC:
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if (bus->mdc) {
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bus->opc <<= 1;
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bus->opc |= bus->mdio & 1;
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if (bus->cnt == 2*2) { |
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bus->cnt = 0;
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bus->addr = 0;
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bus->state = ADDR; |
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} |
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} |
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break;
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case ADDR:
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if (bus->mdc) {
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bus->addr <<= 1;
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bus->addr |= bus->mdio & 1;
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|
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if (bus->cnt == 5*2) { |
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bus->cnt = 0;
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bus->req = 0;
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bus->state = REQ; |
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} |
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} |
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break;
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case REQ:
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if (bus->mdc) {
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bus->req <<= 1;
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bus->req |= bus->mdio & 1;
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if (bus->cnt == 5*2) { |
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bus->cnt = 0;
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bus->state = TURNAROUND; |
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} |
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} |
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break;
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case TURNAROUND:
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if (bus->mdc && bus->cnt == 2*2) { |
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bus->mdio = 0;
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bus->cnt = 0;
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|
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if (bus->opc == 2) { |
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bus->drive = 1;
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mdio_read_req(bus); |
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bus->mdio = bus->data & 1;
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} |
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bus->state = DATA; |
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} |
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break;
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case DATA:
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if (!bus->mdc) {
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if (bus->drive) {
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bus->mdio = !!(bus->data & (1 << 15)); |
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bus->data <<= 1;
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} |
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} else {
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if (!bus->drive) {
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bus->data <<= 1;
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bus->data |= bus->mdio; |
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} |
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if (bus->cnt == 16 * 2) { |
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bus->cnt = 0;
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bus->state = PREAMBLE; |
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if (!bus->drive)
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mdio_write_req(bus); |
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bus->drive = 0;
|
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} |
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} |
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break;
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default:
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break;
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} |
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} |
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|
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/* ETRAX-FS Ethernet MAC block starts here. */
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|
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#define RW_MA0_LO 0x00 |
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#define RW_MA0_HI 0x01 |
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#define RW_MA1_LO 0x02 |
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#define RW_MA1_HI 0x03 |
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#define RW_GA_LO 0x04 |
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#define RW_GA_HI 0x05 |
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#define RW_GEN_CTRL 0x06 |
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#define RW_REC_CTRL 0x07 |
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#define RW_TR_CTRL 0x08 |
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#define RW_CLR_ERR 0x09 |
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#define RW_MGM_CTRL 0x0a |
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#define R_STAT 0x0b |
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#define FS_ETH_MAX_REGS 0x17 |
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|
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struct fs_eth
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{
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CPUState *env; |
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qemu_irq *irq; |
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VLANClientState *vc; |
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int ethregs;
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|
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/* Two addrs in the filter. */
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uint8_t macaddr[2][6]; |
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uint32_t regs[FS_ETH_MAX_REGS]; |
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|
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struct etraxfs_dma_client *dma_out;
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struct etraxfs_dma_client *dma_in;
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|
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/* MDIO bus. */
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struct qemu_mdio mdio_bus;
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unsigned int phyaddr; |
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int duplex_mismatch;
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|
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/* PHY. */
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struct qemu_phy phy;
|
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}; |
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|
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static void eth_validate_duplex(struct fs_eth *eth) |
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{
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struct qemu_phy *phy;
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unsigned int phy_duplex; |
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unsigned int mac_duplex; |
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int new_mm = 0; |
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|
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phy = eth->mdio_bus.devs[eth->phyaddr]; |
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phy_duplex = !!(phy->read(phy, 18) & (1 << 11)); |
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mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
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|
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if (mac_duplex != phy_duplex)
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new_mm = 1;
|
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|
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if (eth->regs[RW_GEN_CTRL] & 1) { |
| 351 |
if (new_mm != eth->duplex_mismatch) {
|
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if (new_mm)
|
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printf("HW: WARNING "
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"ETH duplex mismatch MAC=%d PHY=%d\n",
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mac_duplex, phy_duplex); |
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else
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printf("HW: ETH duplex ok.\n");
|
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} |
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eth->duplex_mismatch = new_mm; |
| 360 |
} |
| 361 |
} |
| 362 |
|
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
| 364 |
{
|
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struct fs_eth *eth = opaque;
|
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uint32_t r = 0;
|
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|
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addr >>= 2;
|
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|
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switch (addr) {
|
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case R_STAT:
|
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r = eth->mdio_bus.mdio & 1;
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break;
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default:
|
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r = eth->regs[addr]; |
| 376 |
D(printf ("%s %x\n", __func__, addr * 4)); |
| 377 |
break;
|
| 378 |
} |
| 379 |
return r;
|
| 380 |
} |
| 381 |
|
| 382 |
static void eth_update_ma(struct fs_eth *eth, int ma) |
| 383 |
{
|
| 384 |
int reg;
|
| 385 |
int i = 0; |
| 386 |
|
| 387 |
ma &= 1;
|
| 388 |
|
| 389 |
reg = RW_MA0_LO; |
| 390 |
if (ma)
|
| 391 |
reg = RW_MA1_LO; |
| 392 |
|
| 393 |
eth->macaddr[ma][i++] = eth->regs[reg]; |
| 394 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
|
| 395 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
|
| 396 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
|
| 397 |
eth->macaddr[ma][i++] = eth->regs[reg + 4];
|
| 398 |
eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8; |
| 399 |
|
| 400 |
D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
|
| 401 |
eth->macaddr[ma][0], eth->macaddr[ma][1], |
| 402 |
eth->macaddr[ma][2], eth->macaddr[ma][3], |
| 403 |
eth->macaddr[ma][4], eth->macaddr[ma][5])); |
| 404 |
} |
| 405 |
|
| 406 |
static void |
| 407 |
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
| 408 |
{
|
| 409 |
struct fs_eth *eth = opaque;
|
| 410 |
|
| 411 |
addr >>= 2;
|
| 412 |
switch (addr)
|
| 413 |
{
|
| 414 |
case RW_MA0_LO:
|
| 415 |
case RW_MA0_HI:
|
| 416 |
eth->regs[addr] = value; |
| 417 |
eth_update_ma(eth, 0);
|
| 418 |
break;
|
| 419 |
case RW_MA1_LO:
|
| 420 |
case RW_MA1_HI:
|
| 421 |
eth->regs[addr] = value; |
| 422 |
eth_update_ma(eth, 1);
|
| 423 |
break;
|
| 424 |
|
| 425 |
case RW_MGM_CTRL:
|
| 426 |
/* Attach an MDIO/PHY abstraction. */
|
| 427 |
if (value & 2) |
| 428 |
eth->mdio_bus.mdio = value & 1;
|
| 429 |
if (eth->mdio_bus.mdc != (value & 4)) { |
| 430 |
mdio_cycle(ð->mdio_bus); |
| 431 |
eth_validate_duplex(eth); |
| 432 |
} |
| 433 |
eth->mdio_bus.mdc = !!(value & 4);
|
| 434 |
break;
|
| 435 |
|
| 436 |
case RW_REC_CTRL:
|
| 437 |
eth->regs[addr] = value; |
| 438 |
eth_validate_duplex(eth); |
| 439 |
break;
|
| 440 |
|
| 441 |
default:
|
| 442 |
eth->regs[addr] = value; |
| 443 |
D(printf ("%s %x %x\n",
|
| 444 |
__func__, addr, value)); |
| 445 |
break;
|
| 446 |
} |
| 447 |
} |
| 448 |
|
| 449 |
/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
|
| 450 |
filter dropping group addresses we have not joined. The filter has 64
|
| 451 |
bits (m). The has function is a simple nible xor of the group addr. */
|
| 452 |
static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) |
| 453 |
{
|
| 454 |
unsigned int hsh; |
| 455 |
int m_individual = eth->regs[RW_REC_CTRL] & 4; |
| 456 |
int match;
|
| 457 |
|
| 458 |
/* First bit on the wire of a MAC address signals multicast or
|
| 459 |
physical address. */
|
| 460 |
if (!m_individual && !sa[0] & 1) |
| 461 |
return 0; |
| 462 |
|
| 463 |
/* Calculate the hash index for the GA registers. */
|
| 464 |
hsh = 0;
|
| 465 |
hsh ^= (*sa) & 0x3f;
|
| 466 |
hsh ^= ((*sa) >> 6) & 0x03; |
| 467 |
++sa; |
| 468 |
hsh ^= ((*sa) << 2) & 0x03c; |
| 469 |
hsh ^= ((*sa) >> 4) & 0xf; |
| 470 |
++sa; |
| 471 |
hsh ^= ((*sa) << 4) & 0x30; |
| 472 |
hsh ^= ((*sa) >> 2) & 0x3f; |
| 473 |
++sa; |
| 474 |
hsh ^= (*sa) & 0x3f;
|
| 475 |
hsh ^= ((*sa) >> 6) & 0x03; |
| 476 |
++sa; |
| 477 |
hsh ^= ((*sa) << 2) & 0x03c; |
| 478 |
hsh ^= ((*sa) >> 4) & 0xf; |
| 479 |
++sa; |
| 480 |
hsh ^= ((*sa) << 4) & 0x30; |
| 481 |
hsh ^= ((*sa) >> 2) & 0x3f; |
| 482 |
|
| 483 |
hsh &= 63;
|
| 484 |
if (hsh > 31) |
| 485 |
match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); |
| 486 |
else
|
| 487 |
match = eth->regs[RW_GA_LO] & (1 << hsh);
|
| 488 |
D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
|
| 489 |
eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); |
| 490 |
return match;
|
| 491 |
} |
| 492 |
|
| 493 |
static int eth_can_receive(void *opaque) |
| 494 |
{
|
| 495 |
return 1; |
| 496 |
} |
| 497 |
|
| 498 |
static void eth_receive(void *opaque, const uint8_t *buf, int size) |
| 499 |
{
|
| 500 |
unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 501 |
struct fs_eth *eth = opaque;
|
| 502 |
int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
| 503 |
int use_ma1 = eth->regs[RW_REC_CTRL] & 2; |
| 504 |
int r_bcast = eth->regs[RW_REC_CTRL] & 8; |
| 505 |
|
| 506 |
if (size < 12) |
| 507 |
return;
|
| 508 |
|
| 509 |
D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
|
| 510 |
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
| 511 |
use_ma0, use_ma1, r_bcast)); |
| 512 |
|
| 513 |
/* Does the frame get through the address filters? */
|
| 514 |
if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) |
| 515 |
&& (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) |
| 516 |
&& (!r_bcast || memcmp(buf, sa_bcast, 6))
|
| 517 |
&& !eth_match_groupaddr(eth, buf)) |
| 518 |
return;
|
| 519 |
|
| 520 |
/* FIXME: Find another way to pass on the fake csum. */
|
| 521 |
etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1); |
| 522 |
} |
| 523 |
|
| 524 |
static int eth_tx_push(void *opaque, unsigned char *buf, int len) |
| 525 |
{
|
| 526 |
struct fs_eth *eth = opaque;
|
| 527 |
|
| 528 |
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
|
| 529 |
qemu_send_packet(eth->vc, buf, len); |
| 530 |
return len;
|
| 531 |
} |
| 532 |
|
| 533 |
static CPUReadMemoryFunc *eth_read[] = {
|
| 534 |
NULL, NULL, |
| 535 |
ð_readl, |
| 536 |
}; |
| 537 |
|
| 538 |
static CPUWriteMemoryFunc *eth_write[] = {
|
| 539 |
NULL, NULL, |
| 540 |
ð_writel, |
| 541 |
}; |
| 542 |
|
| 543 |
void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
|
| 544 |
qemu_irq *irq, target_phys_addr_t base) |
| 545 |
{
|
| 546 |
struct etraxfs_dma_client *dma = NULL; |
| 547 |
struct fs_eth *eth = NULL; |
| 548 |
|
| 549 |
dma = qemu_mallocz(sizeof *dma * 2); |
| 550 |
if (!dma)
|
| 551 |
return NULL; |
| 552 |
|
| 553 |
eth = qemu_mallocz(sizeof *eth);
|
| 554 |
if (!eth)
|
| 555 |
goto err;
|
| 556 |
|
| 557 |
dma[0].client.push = eth_tx_push;
|
| 558 |
dma[0].client.opaque = eth;
|
| 559 |
dma[1].client.opaque = eth;
|
| 560 |
dma[1].client.pull = NULL; |
| 561 |
|
| 562 |
eth->env = env; |
| 563 |
eth->irq = irq; |
| 564 |
eth->dma_out = dma; |
| 565 |
eth->dma_in = dma + 1;
|
| 566 |
|
| 567 |
/* Connect the phy. */
|
| 568 |
eth->phyaddr = 1;
|
| 569 |
tdk_init(ð->phy); |
| 570 |
mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr); |
| 571 |
|
| 572 |
eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
|
| 573 |
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
|
| 574 |
|
| 575 |
eth->vc = qemu_new_vlan_client(nd->vlan, nd->model, |
| 576 |
eth_receive, eth_can_receive, eth); |
| 577 |
|
| 578 |
return dma;
|
| 579 |
err:
|
| 580 |
qemu_free(eth); |
| 581 |
qemu_free(dma); |
| 582 |
return NULL; |
| 583 |
} |