root / hw / mipsnet.c @ bf38c1a0
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#include "hw.h" |
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#include "mips.h" |
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#include "net.h" |
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#include "isa.h" |
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|
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//#define DEBUG_MIPSNET_SEND
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//#define DEBUG_MIPSNET_RECEIVE
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//#define DEBUG_MIPSNET_DATA
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//#define DEBUG_MIPSNET_IRQ
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|
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/* MIPSnet register offsets */
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|
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#define MIPSNET_DEV_ID 0x00 |
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#define MIPSNET_BUSY 0x08 |
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#define MIPSNET_RX_DATA_COUNT 0x0c |
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#define MIPSNET_TX_DATA_COUNT 0x10 |
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#define MIPSNET_INT_CTL 0x14 |
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# define MIPSNET_INTCTL_TXDONE 0x00000001 |
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# define MIPSNET_INTCTL_RXDONE 0x00000002 |
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# define MIPSNET_INTCTL_TESTBIT 0x80000000 |
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#define MIPSNET_INTERRUPT_INFO 0x18 |
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#define MIPSNET_RX_DATA_BUFFER 0x1c |
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#define MIPSNET_TX_DATA_BUFFER 0x20 |
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|
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#define MAX_ETH_FRAME_SIZE 1514 |
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|
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typedef struct MIPSnetState { |
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uint32_t busy; |
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uint32_t rx_count; |
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uint32_t rx_read; |
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uint32_t tx_count; |
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uint32_t tx_written; |
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uint32_t intctl; |
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uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; |
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uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; |
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qemu_irq irq; |
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VLANClientState *vc; |
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NICInfo *nd; |
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} MIPSnetState; |
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|
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static void mipsnet_reset(MIPSnetState *s) |
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{ |
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s->busy = 1;
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s->rx_count = 0;
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s->rx_read = 0;
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s->tx_count = 0;
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s->tx_written = 0;
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s->intctl = 0;
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memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
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memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
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} |
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static void mipsnet_update_irq(MIPSnetState *s) |
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{ |
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int isr = !!s->intctl;
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#ifdef DEBUG_MIPSNET_IRQ
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printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
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#endif
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qemu_set_irq(s->irq, isr); |
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} |
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static int mipsnet_buffer_full(MIPSnetState *s) |
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{ |
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if (s->rx_count >= MAX_ETH_FRAME_SIZE)
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return 1; |
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return 0; |
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} |
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|
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static int mipsnet_can_receive(void *opaque) |
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{ |
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MIPSnetState *s = opaque; |
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|
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if (s->busy)
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return 0; |
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return !mipsnet_buffer_full(s);
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} |
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|
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static void mipsnet_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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MIPSnetState *s = opaque; |
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|
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#ifdef DEBUG_MIPSNET_RECEIVE
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printf("mipsnet: receiving len=%d\n", size);
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#endif
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if (!mipsnet_can_receive(opaque))
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return;
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s->busy = 1;
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/* Just accept everything. */
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/* Write packet data. */
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memcpy(s->rx_buffer, buf, size); |
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s->rx_count = size; |
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s->rx_read = 0;
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|
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/* Now we can signal we have received something. */
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s->intctl |= MIPSNET_INTCTL_RXDONE; |
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mipsnet_update_irq(s); |
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} |
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|
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static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr) |
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{ |
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MIPSnetState *s = opaque; |
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int ret = 0; |
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addr &= 0x3f;
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switch (addr) {
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case MIPSNET_DEV_ID:
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ret = be32_to_cpu(0x4d495053); /* MIPS */ |
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break;
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case MIPSNET_DEV_ID + 4: |
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ret = be32_to_cpu(0x4e455430); /* NET0 */ |
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break;
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case MIPSNET_BUSY:
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ret = s->busy; |
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break;
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case MIPSNET_RX_DATA_COUNT:
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ret = s->rx_count; |
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break;
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case MIPSNET_TX_DATA_COUNT:
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ret = s->tx_count; |
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break;
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case MIPSNET_INT_CTL:
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ret = s->intctl; |
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s->intctl &= ~MIPSNET_INTCTL_TESTBIT; |
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break;
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case MIPSNET_INTERRUPT_INFO:
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/* XXX: This seems to be a per-VPE interrupt number. */
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ret = 0;
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break;
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case MIPSNET_RX_DATA_BUFFER:
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if (s->rx_count) {
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s->rx_count--; |
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ret = s->rx_buffer[s->rx_read++]; |
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} |
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break;
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/* Reads as zero. */
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case MIPSNET_TX_DATA_BUFFER:
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default:
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break;
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} |
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#ifdef DEBUG_MIPSNET_DATA
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printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
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#endif
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return ret;
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} |
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static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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MIPSnetState *s = opaque; |
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addr &= 0x3f;
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#ifdef DEBUG_MIPSNET_DATA
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printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch (addr) {
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case MIPSNET_TX_DATA_COUNT:
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s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
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s->tx_written = 0;
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break;
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case MIPSNET_INT_CTL:
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if (val & MIPSNET_INTCTL_TXDONE) {
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s->intctl &= ~MIPSNET_INTCTL_TXDONE; |
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} else if (val & MIPSNET_INTCTL_RXDONE) { |
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s->intctl &= ~MIPSNET_INTCTL_RXDONE; |
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} else if (val & MIPSNET_INTCTL_TESTBIT) { |
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mipsnet_reset(s); |
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s->intctl |= MIPSNET_INTCTL_TESTBIT; |
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} else if (!val) { |
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/* ACK testbit interrupt, flag was cleared on read. */
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} |
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s->busy = !!s->intctl; |
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mipsnet_update_irq(s); |
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break;
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case MIPSNET_TX_DATA_BUFFER:
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s->tx_buffer[s->tx_written++] = val; |
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if (s->tx_written == s->tx_count) {
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/* Send buffer. */
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#ifdef DEBUG_MIPSNET_SEND
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printf("mipsnet: sending len=%d\n", s->tx_count);
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#endif
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qemu_send_packet(s->vc, s->tx_buffer, s->tx_count); |
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s->tx_count = s->tx_written = 0;
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s->intctl |= MIPSNET_INTCTL_TXDONE; |
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s->busy = 1;
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mipsnet_update_irq(s); |
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} |
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break;
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/* Read-only registers */
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case MIPSNET_DEV_ID:
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case MIPSNET_BUSY:
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case MIPSNET_RX_DATA_COUNT:
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case MIPSNET_INTERRUPT_INFO:
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case MIPSNET_RX_DATA_BUFFER:
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default:
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break;
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} |
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} |
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static void mipsnet_save(QEMUFile *f, void *opaque) |
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{ |
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MIPSnetState *s = opaque; |
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qemu_put_be32s(f, &s->busy); |
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qemu_put_be32s(f, &s->rx_count); |
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qemu_put_be32s(f, &s->rx_read); |
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qemu_put_be32s(f, &s->tx_count); |
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qemu_put_be32s(f, &s->tx_written); |
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qemu_put_be32s(f, &s->intctl); |
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qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); |
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qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); |
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} |
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|
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static int mipsnet_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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MIPSnetState *s = opaque; |
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|
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if (version_id > 0) |
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return -EINVAL;
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qemu_get_be32s(f, &s->busy); |
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qemu_get_be32s(f, &s->rx_count); |
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qemu_get_be32s(f, &s->rx_read); |
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qemu_get_be32s(f, &s->tx_count); |
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qemu_get_be32s(f, &s->tx_written); |
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qemu_get_be32s(f, &s->intctl); |
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qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); |
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qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); |
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return 0; |
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} |
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|
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void mipsnet_init (int base, qemu_irq irq, NICInfo *nd) |
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{ |
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MIPSnetState *s; |
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s = qemu_mallocz(sizeof(MIPSnetState));
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if (!s)
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return;
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register_ioport_write(base, 36, 1, mipsnet_ioport_write, s); |
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register_ioport_read(base, 36, 1, mipsnet_ioport_read, s); |
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register_ioport_write(base, 36, 2, mipsnet_ioport_write, s); |
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register_ioport_read(base, 36, 2, mipsnet_ioport_read, s); |
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register_ioport_write(base, 36, 4, mipsnet_ioport_write, s); |
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register_ioport_read(base, 36, 4, mipsnet_ioport_read, s); |
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s->irq = irq; |
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s->nd = nd; |
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if (nd && nd->vlan) {
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s->vc = qemu_new_vlan_client(nd->vlan, nd->model, |
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mipsnet_receive, mipsnet_can_receive, s); |
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} else {
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s->vc = NULL;
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} |
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snprintf(s->vc->info_str, sizeof(s->vc->info_str),
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"mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
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s->nd->macaddr[0],
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s->nd->macaddr[1],
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s->nd->macaddr[2],
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s->nd->macaddr[3],
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s->nd->macaddr[4],
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s->nd->macaddr[5]);
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mipsnet_reset(s); |
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register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s); |
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} |