Revision bfed01fc
| b/cpu-exec.c | ||
|---|---|---|
| 40 | 40 |
//#define DEBUG_EXEC |
| 41 | 41 |
//#define DEBUG_SIGNAL |
| 42 | 42 |
|
| 43 |
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \ |
|
| 44 |
defined(TARGET_ALPHA) |
|
| 45 |
/* XXX: unify with i386 target */ |
|
| 46 | 43 |
void cpu_loop_exit(void) |
| 47 | 44 |
{
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/* NOTE: the register at this point must be saved by hand because |
|
| 46 |
longjmp restore them */ |
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regs_to_env(); |
|
| 48 | 48 |
longjmp(env->jmp_env, 1); |
| 49 | 49 |
} |
| 50 |
#endif |
|
| 50 |
|
|
| 51 | 51 |
#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K)) |
| 52 | 52 |
#define reg_T2 |
| 53 | 53 |
#endif |
| ... | ... | |
| 249 | 249 |
TranslationBlock *tb; |
| 250 | 250 |
uint8_t *tc_ptr; |
| 251 | 251 |
|
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#if defined(TARGET_I386) |
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/* handle exit of HALTED state */ |
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if (env1->hflags & HF_HALTED_MASK) {
|
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/* disable halt condition */ |
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && |
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(env1->eflags & IF_MASK)) {
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env1->hflags &= ~HF_HALTED_MASK; |
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} else {
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return EXCP_HALTED; |
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} |
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} |
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#elif defined(TARGET_PPC) |
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if (env1->halted) {
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if (env1->msr[MSR_EE] && |
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(env1->interrupt_request & CPU_INTERRUPT_HARD)) {
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env1->halted = 0; |
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} else {
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return EXCP_HALTED; |
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} |
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} |
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#elif defined(TARGET_SPARC) |
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if (env1->halted) {
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && |
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(env1->psret != 0)) {
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env1->halted = 0; |
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} else {
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return EXCP_HALTED; |
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} |
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} |
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#elif defined(TARGET_ARM) |
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if (env1->halted) {
|
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/* An interrupt wakes the CPU even if the I and F CPSR bits are |
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set. We use EXITTB to silently wake CPU without causing an |
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actual interrupt. */ |
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if (env1->interrupt_request & |
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(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
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env1->halted = 0; |
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} else {
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return EXCP_HALTED; |
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} |
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} |
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#elif defined(TARGET_MIPS) |
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if (env1->halted) {
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if (env1->interrupt_request & |
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
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env1->halted = 0; |
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} else {
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return EXCP_HALTED; |
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} |
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} |
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#elif defined(TARGET_ALPHA) || defined(TARGET_M68K) |
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if (env1->halted) {
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if (env1->interrupt_request & CPU_INTERRUPT_HARD) {
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env1->halted = 0; |
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} else {
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return EXCP_HALTED; |
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} |
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} |
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#endif |
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if (cpu_halted(env1) == EXCP_HALTED) |
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return EXCP_HALTED; |
|
| 311 | 254 |
|
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cpu_single_env = env1; |
| 313 | 256 |
|
| b/target-alpha/exec.h | ||
|---|---|---|
| 79 | 79 |
|
| 80 | 80 |
void do_interrupt (CPUState *env); |
| 81 | 81 |
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static inline int cpu_halted(CPUState *env) {
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if (!env->halted) |
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return 0; |
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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env->halted = 0; |
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return 0; |
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} |
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return EXCP_HALTED; |
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} |
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|
|
| 82 | 92 |
#endif /* !defined (__ALPHA_EXEC_H__) */ |
| b/target-arm/exec.h | ||
|---|---|---|
| 48 | 48 |
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 49 | 49 |
int is_user, int is_softmmu); |
| 50 | 50 |
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static inline int cpu_halted(CPUState *env) {
|
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if (!env->halted) |
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return 0; |
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/* An interrupt wakes the CPU even if the I and F CPSR bits are |
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set. We use EXITTB to silently wake CPU without causing an |
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actual interrupt. */ |
|
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if (env->interrupt_request & |
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(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
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env->halted = 0; |
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return 0; |
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} |
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return EXCP_HALTED; |
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} |
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|
|
| 51 | 65 |
#if !defined(CONFIG_USER_ONLY) |
| 52 | 66 |
#include "softmmu_exec.h" |
| 53 | 67 |
#endif |
| b/target-i386/exec.h | ||
|---|---|---|
| 575 | 575 |
env->regs[R_EDI] = EDI; |
| 576 | 576 |
#endif |
| 577 | 577 |
} |
| 578 |
|
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static inline int cpu_halted(CPUState *env) {
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/* handle exit of HALTED state */ |
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if (env->hflags & HF_HALTED_MASK) |
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return 0; |
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/* disable halt condition */ |
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if ((env->interrupt_request & CPU_INTERRUPT_HARD) && |
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(env->eflags & IF_MASK)) {
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env->hflags &= ~HF_HALTED_MASK; |
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return 0; |
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} |
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return EXCP_HALTED; |
|
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} |
|
| b/target-i386/helper.c | ||
|---|---|---|
| 106 | 106 |
spin_unlock(&global_cpu_lock); |
| 107 | 107 |
} |
| 108 | 108 |
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void cpu_loop_exit(void) |
|
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{
|
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/* NOTE: the register at this point must be saved by hand because |
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longjmp restore them */ |
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regs_to_env(); |
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longjmp(env->jmp_env, 1); |
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} |
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|
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| 117 | 109 |
/* return non zero if error */ |
| 118 | 110 |
static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr, |
| 119 | 111 |
int selector) |
| b/target-m68k/exec.h | ||
|---|---|---|
| 49 | 49 |
void helper_movec(CPUM68KState *env, int reg, uint32_t val); |
| 50 | 50 |
|
| 51 | 51 |
void cpu_loop_exit(void); |
| 52 |
|
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static inline int cpu_halted(CPUState *env) {
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if (!env->halted) |
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return 0; |
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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env->halted = 0; |
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return 0; |
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} |
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return EXCP_HALTED; |
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} |
|
| b/target-mips/exec.h | ||
|---|---|---|
| 56 | 56 |
#include "softmmu_exec.h" |
| 57 | 57 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
| 58 | 58 |
|
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static inline void env_to_regs(void) |
|
| 60 |
{
|
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} |
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|
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static inline void regs_to_env(void) |
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{
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} |
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|
|
| 67 | 59 |
#ifdef TARGET_MIPS64 |
| 68 | 60 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| 69 | 61 |
void do_dsll (void); |
| ... | ... | |
| 240 | 232 |
FOP_PROTO(ngt) |
| 241 | 233 |
#undef FOP_PROTO |
| 242 | 234 |
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static inline void env_to_regs(void) |
|
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{
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} |
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|
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static inline void regs_to_env(void) |
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{
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} |
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|
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static inline int cpu_halted(CPUState *env) {
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if (!env->halted) |
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return 0; |
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if (env->interrupt_request & |
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
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env->halted = 0; |
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return 0; |
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} |
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return EXCP_HALTED; |
|
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} |
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|
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| 243 | 254 |
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 24 | 24 |
|
| 25 | 25 |
/*****************************************************************************/ |
| 26 | 26 |
/* Exceptions processing helpers */ |
| 27 |
void cpu_loop_exit(void) |
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{
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longjmp(env->jmp_env, 1); |
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} |
|
| 31 | 27 |
|
| 32 | 28 |
void do_raise_exception_err (uint32_t exception, int error_code) |
| 33 | 29 |
{
|
| b/target-ppc/exec.h | ||
|---|---|---|
| 122 | 122 |
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 123 | 123 |
int is_user, int is_softmmu); |
| 124 | 124 |
|
| 125 |
static inline int cpu_halted(CPUState *env) {
|
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if (!env->halted) |
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return 0; |
|
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if (env->msr[MSR_EE] && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
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env->halted = 0; |
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return 0; |
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} |
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return EXCP_HALTED; |
|
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} |
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|
|
| 125 | 135 |
#endif /* !defined (__PPC_H__) */ |
| b/target-ppc/op_helper.c | ||
|---|---|---|
| 40 | 40 |
|
| 41 | 41 |
/*****************************************************************************/ |
| 42 | 42 |
/* Exceptions processing helpers */ |
| 43 |
void cpu_loop_exit (void) |
|
| 44 |
{
|
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| 45 |
longjmp(env->jmp_env, 1); |
|
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} |
|
| 47 | 43 |
|
| 48 | 44 |
void do_raise_exception_err (uint32_t exception, int error_code) |
| 49 | 45 |
{
|
| b/target-sh4/op_helper.c | ||
|---|---|---|
| 20 | 20 |
#include <assert.h> |
| 21 | 21 |
#include "exec.h" |
| 22 | 22 |
|
| 23 |
void cpu_loop_exit(void) |
|
| 24 |
{
|
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| 25 |
longjmp(env->jmp_env, 1); |
|
| 26 |
} |
|
| 27 |
|
|
| 28 | 23 |
void do_raise_exception(void) |
| 29 | 24 |
{
|
| 30 | 25 |
cpu_loop_exit(); |
| b/target-sparc/exec.h | ||
|---|---|---|
| 115 | 115 |
int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
| 116 | 116 |
int is_user, int is_softmmu); |
| 117 | 117 |
|
| 118 |
static inline int cpu_halted(CPUState *env) {
|
|
| 119 |
if (!env->halted) |
|
| 120 |
return 0; |
|
| 121 |
if ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psret != 0)) {
|
|
| 122 |
env->halted = 0; |
|
| 123 |
return 0; |
|
| 124 |
} |
|
| 125 |
return EXCP_HALTED; |
|
| 126 |
} |
|
| 127 |
|
|
| 118 | 128 |
#endif |
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