/ - Diff - qemu - Greek Research and Technology Network's projects

Revision c01fccd2

         uint32_t nb_tlb;
         uint32_t tlb_in_use;
         int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
         void (*do_tlbwi) (void);
         void (*do_tlbwr) (void);
         void (*do_tlbp) (void);
         void (*do_tlbr) (void);
         void (*helper_tlbwi) (void);
         void (*helper_tlbwr) (void);
         void (*helper_tlbp) (void);
         void (*helper_tlbr) (void);
         union {
             struct {
                 r4k_tlb_t tlb[MIPS_TLB_MAX];
-...
                                target_ulong address, int rw, int access_type);
     int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                          target_ulong address, int rw, int access_type);
     void r4k_do_tlbwi (void);
     void r4k_do_tlbwr (void);
     void r4k_do_tlbp (void);
     void r4k_do_tlbr (void);
     void r4k_helper_tlbwi (void);
     void r4k_helper_tlbwr (void);
     void r4k_helper_tlbp (void);
     void r4k_helper_tlbr (void);
     void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
     void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

     #include "softmmu_exec.h"
     #endif /* !defined(CONFIG_USER_ONLY) */
     void do_mtc0_status_debug(uint32_t old, uint32_t val);
     void do_mtc0_status_irqraise_debug(void);
     void dump_fpu(CPUState *env);
     void fpu_dump_state(CPUState *env, FILE *f,
                         int (*fpu_fprintf)(FILE *f, const char *fmt, ...),

     #include "def-helper.h"
     /* FIXME: We should rename the helper functions and remove this hack.  */
     #undef HELPER
     #define HELPER(name) do_##name
     DEF_HELPER_2(raise_exception_err, void, i32, int)
     DEF_HELPER_1(raise_exception, void, i32)
     DEF_HELPER_0(interrupt_restart, void)

b/target-mips/op_helper.c
26	26	/*****************************************************************************/
27	27	/* Exceptions processing helpers */
28	28
29		void do_raise_exception_err (uint32_t exception, int error_code)
	29	void helper_raise_exception_err (uint32_t exception, int error_code)
30	30	{
31	31	#if 1
32	32	if (exception < 0x100)
...	...
37	37	cpu_loop_exit();
38	38	}
39	39
40		void do_raise_exception (uint32_t exception)
	40	void helper_raise_exception (uint32_t exception)
41	41	{
42		do_raise_exception_err(exception, 0);
	42	helper_raise_exception_err(exception, 0);
43	43	}
44	44
45		void do_interrupt_restart (void)
	45	void helper_interrupt_restart (void)
46	46	{
47	47	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
48	48	!(env->CP0_Status & (1 << CP0St_ERL)) &&
...	...
50	50	(env->CP0_Status & (1 << CP0St_IE)) &&
51	51	(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
52	52	env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
53		do_raise_exception(EXCP_EXT_INTERRUPT);
	53	helper_raise_exception(EXCP_EXT_INTERRUPT);
54	54	}
55	55	}
56	56
...	...
67	67	}
68	68	#endif
69	69
70		target_ulong do_clo (target_ulong t0)
	70	target_ulong helper_clo (target_ulong t0)
71	71	{
72	72	return clo32(t0);
73	73	}
74	74
75		target_ulong do_clz (target_ulong t0)
	75	target_ulong helper_clz (target_ulong t0)
76	76	{
77	77	return clz32(t0);
78	78	}
79	79
80	80	#if defined(TARGET_MIPS64)
81		target_ulong do_dclo (target_ulong t0)
	81	target_ulong helper_dclo (target_ulong t0)
82	82	{
83	83	return clo64(t0);
84	84	}
85	85
86		target_ulong do_dclz (target_ulong t0)
	86	target_ulong helper_dclz (target_ulong t0)
87	87	{
88	88	return clz64(t0);
89	89	}
...	...
114	114	}
115	115
116	116	#if TARGET_LONG_BITS > HOST_LONG_BITS
117		void do_madd (target_ulong t0, target_ulong t1)
	117	void helper_madd (target_ulong t0, target_ulong t1)
118	118	{
119	119	int64_t tmp;
120	120
...	...
122	122	set_HILO((int64_t)get_HILO() + tmp);
123	123	}
124	124
125		void do_maddu (target_ulong t0, target_ulong t1)
	125	void helper_maddu (target_ulong t0, target_ulong t1)
126	126	{
127	127	uint64_t tmp;
128	128
...	...
130	130	set_HILO(get_HILO() + tmp);
131	131	}
132	132
133		void do_msub (target_ulong t0, target_ulong t1)
	133	void helper_msub (target_ulong t0, target_ulong t1)
134	134	{
135	135	int64_t tmp;
136	136
...	...
138	138	set_HILO((int64_t)get_HILO() - tmp);
139	139	}
140	140
141		void do_msubu (target_ulong t0, target_ulong t1)
	141	void helper_msubu (target_ulong t0, target_ulong t1)
142	142	{
143	143	uint64_t tmp;
144	144
...	...
148	148	#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
149	149
150	150	/* Multiplication variants of the vr54xx. */
151		target_ulong do_muls (target_ulong t0, target_ulong t1)
	151	target_ulong helper_muls (target_ulong t0, target_ulong t1)
152	152	{
153	153	set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
154	154
155	155	return t0;
156	156	}
157	157
158		target_ulong do_mulsu (target_ulong t0, target_ulong t1)
	158	target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
159	159	{
160	160	set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
161	161
162	162	return t0;
163	163	}
164	164
165		target_ulong do_macc (target_ulong t0, target_ulong t1)
	165	target_ulong helper_macc (target_ulong t0, target_ulong t1)
166	166	{
167	167	set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
168	168
169	169	return t0;
170	170	}
171	171
172		target_ulong do_macchi (target_ulong t0, target_ulong t1)
	172	target_ulong helper_macchi (target_ulong t0, target_ulong t1)
173	173	{
174	174	set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
175	175
176	176	return t0;
177	177	}
178	178
179		target_ulong do_maccu (target_ulong t0, target_ulong t1)
	179	target_ulong helper_maccu (target_ulong t0, target_ulong t1)
180	180	{
181	181	set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
182	182
183	183	return t0;
184	184	}
185	185
186		target_ulong do_macchiu (target_ulong t0, target_ulong t1)
	186	target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
187	187	{
188	188	set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
189	189
190	190	return t0;
191	191	}
192	192
193		target_ulong do_msac (target_ulong t0, target_ulong t1)
	193	target_ulong helper_msac (target_ulong t0, target_ulong t1)
194	194	{
195	195	set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
196	196
197	197	return t0;
198	198	}
199	199
200		target_ulong do_msachi (target_ulong t0, target_ulong t1)
	200	target_ulong helper_msachi (target_ulong t0, target_ulong t1)
201	201	{
202	202	set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
203	203
204	204	return t0;
205	205	}
206	206
207		target_ulong do_msacu (target_ulong t0, target_ulong t1)
	207	target_ulong helper_msacu (target_ulong t0, target_ulong t1)
208	208	{
209	209	set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
210	210
211	211	return t0;
212	212	}
213	213
214		target_ulong do_msachiu (target_ulong t0, target_ulong t1)
	214	target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
215	215	{
216	216	set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
217	217
218	218	return t0;
219	219	}
220	220
221		target_ulong do_mulhi (target_ulong t0, target_ulong t1)
	221	target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
222	222	{
223	223	set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
224	224
225	225	return t0;
226	226	}
227	227
228		target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
	228	target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
229	229	{
230	230	set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
231	231
232	232	return t0;
233	233	}
234	234
235		target_ulong do_mulshi (target_ulong t0, target_ulong t1)
	235	target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
236	236	{
237	237	set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
238	238
239	239	return t0;
240	240	}
241	241
242		target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
	242	target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
243	243	{
244	244	set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
245	245
...	...
247	247	}
248	248
249	249	#ifdef TARGET_MIPS64
250		void do_dmult (target_ulong t0, target_ulong t1)
	250	void helper_dmult (target_ulong t0, target_ulong t1)
251	251	{
252	252	muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
253	253	}
254	254
255		void do_dmultu (target_ulong t0, target_ulong t1)
	255	void helper_dmultu (target_ulong t0, target_ulong t1)
256	256	{
257	257	mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
258	258	}
...	...
266	266	#define GET_OFFSET(addr, offset) (addr - (offset))
267	267	#endif
268	268
269		target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
	269	target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
270	270	{
271	271	target_ulong tmp;
272	272
...	...
303	303	return (int32_t)t1;
304	304	}
305	305
306		target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
	306	target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
307	307	{
308	308	target_ulong tmp;
309	309
...	...
340	340	return (int32_t)t1;
341	341	}
342	342
343		void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
	343	void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
344	344	{
345	345	#ifdef CONFIG_USER_ONLY
346	346	#define stfun stb_raw
...	...
367	367	stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
368	368	}
369	369
370		void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
	370	void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
371	371	{
372	372	#ifdef CONFIG_USER_ONLY
373	373	#define stfun stb_raw
...	...
404	404	#define GET_LMASK64(v) (((v) & 7) ^ 7)
405	405	#endif
406	406
407		target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
	407	target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
408	408	{
409	409	uint64_t tmp;
410	410
...	...
462	462	return t1;
463	463	}
464	464
465		target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
	465	target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
466	466	{
467	467	uint64_t tmp;
468	468
...	...
520	520	return t1;
521	521	}
522	522
523		void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
	523	void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
524	524	{
525	525	#ifdef CONFIG_USER_ONLY
526	526	#define stfun stb_raw
...	...
559	559	stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
560	560	}
561	561
562		void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
	562	void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
563	563	{
564	564	#ifdef CONFIG_USER_ONLY
565	565	#define stfun stb_raw
...	...
601	601
602	602	#ifndef CONFIG_USER_ONLY
603	603	/* CP0 helpers */
604		target_ulong do_mfc0_mvpcontrol (void)
	604	target_ulong helper_mfc0_mvpcontrol (void)
605	605	{
606	606	return env->mvp->CP0_MVPControl;
607	607	}
608	608
609		target_ulong do_mfc0_mvpconf0 (void)
	609	target_ulong helper_mfc0_mvpconf0 (void)
610	610	{
611	611	return env->mvp->CP0_MVPConf0;
612	612	}
613	613
614		target_ulong do_mfc0_mvpconf1 (void)
	614	target_ulong helper_mfc0_mvpconf1 (void)
615	615	{
616	616	return env->mvp->CP0_MVPConf1;
617	617	}
618	618
619		target_ulong do_mfc0_random (void)
	619	target_ulong helper_mfc0_random (void)
620	620	{
621	621	return (int32_t)cpu_mips_get_random(env);
622	622	}
623	623
624		target_ulong do_mfc0_tcstatus (void)
	624	target_ulong helper_mfc0_tcstatus (void)
625	625	{
626	626	return env->active_tc.CP0_TCStatus;
627	627	}
628	628
629		target_ulong do_mftc0_tcstatus(void)
	629	target_ulong helper_mftc0_tcstatus(void)
630	630	{
631	631	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
632	632
...	...
636	636	return env->tcs[other_tc].CP0_TCStatus;
637	637	}
638	638
639		target_ulong do_mfc0_tcbind (void)
	639	target_ulong helper_mfc0_tcbind (void)
640	640	{
641	641	return env->active_tc.CP0_TCBind;
642	642	}
643	643
644		target_ulong do_mftc0_tcbind(void)
	644	target_ulong helper_mftc0_tcbind(void)
645	645	{
646	646	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
647	647
...	...
651	651	return env->tcs[other_tc].CP0_TCBind;
652	652	}
653	653
654		target_ulong do_mfc0_tcrestart (void)
	654	target_ulong helper_mfc0_tcrestart (void)
655	655	{
656	656	return env->active_tc.PC;
657	657	}
658	658
659		target_ulong do_mftc0_tcrestart(void)
	659	target_ulong helper_mftc0_tcrestart(void)
660	660	{
661	661	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
662	662
...	...
666	666	return env->tcs[other_tc].PC;
667	667	}
668	668
669		target_ulong do_mfc0_tchalt (void)
	669	target_ulong helper_mfc0_tchalt (void)
670	670	{
671	671	return env->active_tc.CP0_TCHalt;
672	672	}
673	673
674		target_ulong do_mftc0_tchalt(void)
	674	target_ulong helper_mftc0_tchalt(void)
675	675	{
676	676	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
677	677
...	...
681	681	return env->tcs[other_tc].CP0_TCHalt;
682	682	}
683	683
684		target_ulong do_mfc0_tccontext (void)
	684	target_ulong helper_mfc0_tccontext (void)
685	685	{
686	686	return env->active_tc.CP0_TCContext;
687	687	}
688	688
689		target_ulong do_mftc0_tccontext(void)
	689	target_ulong helper_mftc0_tccontext(void)
690	690	{
691	691	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
692	692
...	...
696	696	return env->tcs[other_tc].CP0_TCContext;
697	697	}
698	698
699		target_ulong do_mfc0_tcschedule (void)
	699	target_ulong helper_mfc0_tcschedule (void)
700	700	{
701	701	return env->active_tc.CP0_TCSchedule;
702	702	}
703	703
704		target_ulong do_mftc0_tcschedule(void)
	704	target_ulong helper_mftc0_tcschedule(void)
705	705	{
706	706	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
707	707
...	...
711	711	return env->tcs[other_tc].CP0_TCSchedule;
712	712	}
713	713
714		target_ulong do_mfc0_tcschefback (void)
	714	target_ulong helper_mfc0_tcschefback (void)
715	715	{
716	716	return env->active_tc.CP0_TCScheFBack;
717	717	}
718	718
719		target_ulong do_mftc0_tcschefback(void)
	719	target_ulong helper_mftc0_tcschefback(void)
720	720	{
721	721	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
722	722
...	...
726	726	return env->tcs[other_tc].CP0_TCScheFBack;
727	727	}
728	728
729		target_ulong do_mfc0_count (void)
	729	target_ulong helper_mfc0_count (void)
730	730	{
731	731	return (int32_t)cpu_mips_get_count(env);
732	732	}
733	733
734		target_ulong do_mftc0_entryhi(void)
	734	target_ulong helper_mftc0_entryhi(void)
735	735	{
736	736	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
737	737	int32_t tcstatus;
...	...
744	744	return (env->CP0_EntryHi & ~0xff) \| (tcstatus & 0xff);
745	745	}
746	746
747		target_ulong do_mftc0_status(void)
	747	target_ulong helper_mftc0_status(void)
748	748	{
749	749	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
750	750	target_ulong t0;
...	...
763	763	return t0;
764	764	}
765	765
766		target_ulong do_mfc0_lladdr (void)
	766	target_ulong helper_mfc0_lladdr (void)
767	767	{
768	768	return (int32_t)env->CP0_LLAddr >> 4;
769	769	}
770	770
771		target_ulong do_mfc0_watchlo (uint32_t sel)
	771	target_ulong helper_mfc0_watchlo (uint32_t sel)
772	772	{
773	773	return (int32_t)env->CP0_WatchLo[sel];
774	774	}
775	775
776		target_ulong do_mfc0_watchhi (uint32_t sel)
	776	target_ulong helper_mfc0_watchhi (uint32_t sel)
777	777	{
778	778	return env->CP0_WatchHi[sel];
779	779	}
780	780
781		target_ulong do_mfc0_debug (void)
	781	target_ulong helper_mfc0_debug (void)
782	782	{
783	783	target_ulong t0 = env->CP0_Debug;
784	784	if (env->hflags & MIPS_HFLAG_DM)
...	...
787	787	return t0;
788	788	}
789	789
790		target_ulong do_mftc0_debug(void)
	790	target_ulong helper_mftc0_debug(void)
791	791	{
792	792	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
793	793	int32_t tcstatus;
...	...
803	803	}
804	804
805	805	#if defined(TARGET_MIPS64)
806		target_ulong do_dmfc0_tcrestart (void)
	806	target_ulong helper_dmfc0_tcrestart (void)
807	807	{
808	808	return env->active_tc.PC;
809	809	}
810	810
811		target_ulong do_dmfc0_tchalt (void)
	811	target_ulong helper_dmfc0_tchalt (void)
812	812	{
813	813	return env->active_tc.CP0_TCHalt;
814	814	}
815	815
816		target_ulong do_dmfc0_tccontext (void)
	816	target_ulong helper_dmfc0_tccontext (void)
817	817	{
818	818	return env->active_tc.CP0_TCContext;
819	819	}
820	820
821		target_ulong do_dmfc0_tcschedule (void)
	821	target_ulong helper_dmfc0_tcschedule (void)
822	822	{
823	823	return env->active_tc.CP0_TCSchedule;
824	824	}
825	825
826		target_ulong do_dmfc0_tcschefback (void)
	826	target_ulong helper_dmfc0_tcschefback (void)
827	827	{
828	828	return env->active_tc.CP0_TCScheFBack;
829	829	}
830	830
831		target_ulong do_dmfc0_lladdr (void)
	831	target_ulong helper_dmfc0_lladdr (void)
832	832	{
833	833	return env->CP0_LLAddr >> 4;
834	834	}
835	835
836		target_ulong do_dmfc0_watchlo (uint32_t sel)
	836	target_ulong helper_dmfc0_watchlo (uint32_t sel)
837	837	{
838	838	return env->CP0_WatchLo[sel];
839	839	}
840	840	#endif /* TARGET_MIPS64 */
841	841
842		void do_mtc0_index (target_ulong t0)
	842	void helper_mtc0_index (target_ulong t0)
843	843	{
844	844	int num = 1;
845	845	unsigned int tmp = env->tlb->nb_tlb;
...	...
851	851	env->CP0_Index = (env->CP0_Index & 0x80000000) \| (t0 & (num - 1));
852	852	}
853	853
854		void do_mtc0_mvpcontrol (target_ulong t0)
	854	void helper_mtc0_mvpcontrol (target_ulong t0)
855	855	{
856	856	uint32_t mask = 0;
857	857	uint32_t newval;
...	...
868	868	env->mvp->CP0_MVPControl = newval;
869	869	}
870	870
871		void do_mtc0_vpecontrol (target_ulong t0)
	871	void helper_mtc0_vpecontrol (target_ulong t0)
872	872	{
873	873	uint32_t mask;
874	874	uint32_t newval;
...	...
885	885	env->CP0_VPEControl = newval;
886	886	}
887	887
888		void do_mtc0_vpeconf0 (target_ulong t0)
	888	void helper_mtc0_vpeconf0 (target_ulong t0)
889	889	{
890	890	uint32_t mask = 0;
891	891	uint32_t newval;
...	...
902	902	env->CP0_VPEConf0 = newval;
903	903	}
904	904
905		void do_mtc0_vpeconf1 (target_ulong t0)
	905	void helper_mtc0_vpeconf1 (target_ulong t0)
906	906	{
907	907	uint32_t mask = 0;
908	908	uint32_t newval;
...	...
920	920	env->CP0_VPEConf1 = newval;
921	921	}
922	922
923		void do_mtc0_yqmask (target_ulong t0)
	923	void helper_mtc0_yqmask (target_ulong t0)
924	924	{
925	925	/* Yield qualifier inputs not implemented. */
926	926	env->CP0_YQMask = 0x00000000;
927	927	}
928	928
929		void do_mtc0_vpeopt (target_ulong t0)
	929	void helper_mtc0_vpeopt (target_ulong t0)
930	930	{
931	931	env->CP0_VPEOpt = t0 & 0x0000ffff;
932	932	}
933	933
934		void do_mtc0_entrylo0 (target_ulong t0)
	934	void helper_mtc0_entrylo0 (target_ulong t0)
935	935	{
936	936	/* Large physaddr (PABITS) not implemented */
937	937	/* 1k pages not implemented */
938	938	env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
939	939	}
940	940
941		void do_mtc0_tcstatus (target_ulong t0)
	941	void helper_mtc0_tcstatus (target_ulong t0)
942	942	{
943	943	uint32_t mask = env->CP0_TCStatus_rw_bitmask;
944	944	uint32_t newval;
...	...
950	950	env->active_tc.CP0_TCStatus = newval;
951	951	}
952	952
953		void do_mttc0_tcstatus (target_ulong t0)
	953	void helper_mttc0_tcstatus (target_ulong t0)
954	954	{
955	955	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
956	956
...	...
962	962	env->tcs[other_tc].CP0_TCStatus = t0;
963	963	}
964	964
965		void do_mtc0_tcbind (target_ulong t0)
	965	void helper_mtc0_tcbind (target_ulong t0)
966	966	{
967	967	uint32_t mask = (1 << CP0TCBd_TBE);
968	968	uint32_t newval;
...	...
973	973	env->active_tc.CP0_TCBind = newval;
974	974	}
975	975
976		void do_mttc0_tcbind (target_ulong t0)
	976	void helper_mttc0_tcbind (target_ulong t0)
977	977	{
978	978	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
979	979	uint32_t mask = (1 << CP0TCBd_TBE);
...	...
990	990	}
991	991	}
992	992
993		void do_mtc0_tcrestart (target_ulong t0)
	993	void helper_mtc0_tcrestart (target_ulong t0)
994	994	{
995	995	env->active_tc.PC = t0;
996	996	env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
...	...
998	998	/* MIPS16 not implemented. */
999	999	}
1000	1000
1001		void do_mttc0_tcrestart (target_ulong t0)
	1001	void helper_mttc0_tcrestart (target_ulong t0)
1002	1002	{
1003	1003	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1004	1004
...	...
1015	1015	}
1016	1016	}
1017	1017
1018		void do_mtc0_tchalt (target_ulong t0)
	1018	void helper_mtc0_tchalt (target_ulong t0)
1019	1019	{
1020	1020	env->active_tc.CP0_TCHalt = t0 & 0x1;
1021	1021
1022	1022	// TODO: Halt TC / Restart (if allocated+active) TC.
1023	1023	}
1024	1024
1025		void do_mttc0_tchalt (target_ulong t0)
	1025	void helper_mttc0_tchalt (target_ulong t0)
1026	1026	{
1027	1027	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1028	1028
...	...
1034	1034	env->tcs[other_tc].CP0_TCHalt = t0;
1035	1035	}
1036	1036
1037		void do_mtc0_tccontext (target_ulong t0)
	1037	void helper_mtc0_tccontext (target_ulong t0)
1038	1038	{
1039	1039	env->active_tc.CP0_TCContext = t0;
1040	1040	}
1041	1041
1042		void do_mttc0_tccontext (target_ulong t0)
	1042	void helper_mttc0_tccontext (target_ulong t0)
1043	1043	{
1044	1044	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1045	1045
...	...
1049	1049	env->tcs[other_tc].CP0_TCContext = t0;
1050	1050	}
1051	1051
1052		void do_mtc0_tcschedule (target_ulong t0)
	1052	void helper_mtc0_tcschedule (target_ulong t0)
1053	1053	{
1054	1054	env->active_tc.CP0_TCSchedule = t0;
1055	1055	}
1056	1056
1057		void do_mttc0_tcschedule (target_ulong t0)
	1057	void helper_mttc0_tcschedule (target_ulong t0)
1058	1058	{
1059	1059	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1060	1060
...	...
1064	1064	env->tcs[other_tc].CP0_TCSchedule = t0;
1065	1065	}
1066	1066
1067		void do_mtc0_tcschefback (target_ulong t0)
	1067	void helper_mtc0_tcschefback (target_ulong t0)
1068	1068	{
1069	1069	env->active_tc.CP0_TCScheFBack = t0;
1070	1070	}
1071	1071
1072		void do_mttc0_tcschefback (target_ulong t0)
	1072	void helper_mttc0_tcschefback (target_ulong t0)
1073	1073	{
1074	1074	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1075	1075
...	...
1079	1079	env->tcs[other_tc].CP0_TCScheFBack = t0;
1080	1080	}
1081	1081
1082		void do_mtc0_entrylo1 (target_ulong t0)
	1082	void helper_mtc0_entrylo1 (target_ulong t0)
1083	1083	{
1084	1084	/* Large physaddr (PABITS) not implemented */
1085	1085	/* 1k pages not implemented */
1086	1086	env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
1087	1087	}
1088	1088
1089		void do_mtc0_context (target_ulong t0)
	1089	void helper_mtc0_context (target_ulong t0)
1090	1090	{
1091	1091	env->CP0_Context = (env->CP0_Context & 0x007FFFFF) \| (t0 & ~0x007FFFFF);
1092	1092	}
1093	1093
1094		void do_mtc0_pagemask (target_ulong t0)
	1094	void helper_mtc0_pagemask (target_ulong t0)
1095	1095	{
1096	1096	/* 1k pages not implemented */
1097	1097	env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1098	1098	}
1099	1099
1100		void do_mtc0_pagegrain (target_ulong t0)
	1100	void helper_mtc0_pagegrain (target_ulong t0)
1101	1101	{
1102	1102	/* SmartMIPS not implemented */
1103	1103	/* Large physaddr (PABITS) not implemented */
...	...
1105	1105	env->CP0_PageGrain = 0;
1106	1106	}
1107	1107
1108		void do_mtc0_wired (target_ulong t0)
	1108	void helper_mtc0_wired (target_ulong t0)
1109	1109	{
1110	1110	env->CP0_Wired = t0 % env->tlb->nb_tlb;
1111	1111	}
1112	1112
1113		void do_mtc0_srsconf0 (target_ulong t0)
	1113	void helper_mtc0_srsconf0 (target_ulong t0)
1114	1114	{
1115	1115	env->CP0_SRSConf0 \|= t0 & env->CP0_SRSConf0_rw_bitmask;
1116	1116	}
1117	1117
1118		void do_mtc0_srsconf1 (target_ulong t0)
	1118	void helper_mtc0_srsconf1 (target_ulong t0)
1119	1119	{
1120	1120	env->CP0_SRSConf1 \|= t0 & env->CP0_SRSConf1_rw_bitmask;
1121	1121	}
1122	1122
1123		void do_mtc0_srsconf2 (target_ulong t0)
	1123	void helper_mtc0_srsconf2 (target_ulong t0)
1124	1124	{
1125	1125	env->CP0_SRSConf2 \|= t0 & env->CP0_SRSConf2_rw_bitmask;
1126	1126	}
1127	1127
1128		void do_mtc0_srsconf3 (target_ulong t0)
	1128	void helper_mtc0_srsconf3 (target_ulong t0)
1129	1129	{
1130	1130	env->CP0_SRSConf3 \|= t0 & env->CP0_SRSConf3_rw_bitmask;
1131	1131	}
1132	1132
1133		void do_mtc0_srsconf4 (target_ulong t0)
	1133	void helper_mtc0_srsconf4 (target_ulong t0)
1134	1134	{
1135	1135	env->CP0_SRSConf4 \|= t0 & env->CP0_SRSConf4_rw_bitmask;
1136	1136	}
1137	1137
1138		void do_mtc0_hwrena (target_ulong t0)
	1138	void helper_mtc0_hwrena (target_ulong t0)
1139	1139	{
1140	1140	env->CP0_HWREna = t0 & 0x0000000F;
1141	1141	}
1142	1142
1143		void do_mtc0_count (target_ulong t0)
	1143	void helper_mtc0_count (target_ulong t0)
1144	1144	{
1145	1145	cpu_mips_store_count(env, t0);
1146	1146	}
1147	1147
1148		void do_mtc0_entryhi (target_ulong t0)
	1148	void helper_mtc0_entryhi (target_ulong t0)
1149	1149	{
1150	1150	target_ulong old, val;
1151	1151
...	...
1165	1165	cpu_mips_tlb_flush(env, 1);
1166	1166	}
1167	1167
1168		void do_mttc0_entryhi(target_ulong t0)
	1168	void helper_mttc0_entryhi(target_ulong t0)
1169	1169	{
1170	1170	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1171	1171	int32_t tcstatus;
...	...
1180	1180	}
1181	1181	}
1182	1182
1183		void do_mtc0_compare (target_ulong t0)
	1183	void helper_mtc0_compare (target_ulong t0)
1184	1184	{
1185	1185	cpu_mips_store_compare(env, t0);
1186	1186	}
1187	1187
1188		void do_mtc0_status (target_ulong t0)
	1188	void helper_mtc0_status (target_ulong t0)
1189	1189	{
1190	1190	uint32_t val, old;
1191	1191	uint32_t mask = env->CP0_Status_rw_bitmask;
...	...
1194	1194	old = env->CP0_Status;
1195	1195	env->CP0_Status = (env->CP0_Status & ~mask) \| val;
1196	1196	compute_hflags(env);
1197		if (qemu_loglevel_mask(CPU_LOG_EXEC))
1198		do_mtc0_status_debug(old, val);
	1197	if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
	1198	qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
	1199	old, old & env->CP0_Cause & CP0Ca_IP_mask,
	1200	val, val & env->CP0_Cause & CP0Ca_IP_mask,
	1201	env->CP0_Cause);
	1202	switch (env->hflags & MIPS_HFLAG_KSU) {
	1203	case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
	1204	case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
	1205	case MIPS_HFLAG_KM: qemu_log("\n"); break;
	1206	default: cpu_abort(env, "Invalid MMU mode!\n"); break;
	1207	}
	1208	}
1199	1209	cpu_mips_update_irq(env);
1200	1210	}
1201	1211
1202		void do_mttc0_status(target_ulong t0)
	1212	void helper_mttc0_status(target_ulong t0)
1203	1213	{
1204	1214	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1205	1215	int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
...	...
1214	1224	env->tcs[other_tc].CP0_TCStatus = tcstatus;
1215	1225	}
1216	1226
1217		void do_mtc0_intctl (target_ulong t0)
	1227	void helper_mtc0_intctl (target_ulong t0)
1218	1228	{
1219	1229	/* vectored interrupts not implemented, no performance counters. */
1220	1230	env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) \| (t0 & 0x000002e0);
1221	1231	}
1222	1232
1223		void do_mtc0_srsctl (target_ulong t0)
	1233	void helper_mtc0_srsctl (target_ulong t0)
1224	1234	{
1225	1235	uint32_t mask = (0xf << CP0SRSCtl_ESS) \| (0xf << CP0SRSCtl_PSS);
1226	1236	env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) \| (t0 & mask);
1227	1237	}
1228	1238
1229		void do_mtc0_cause (target_ulong t0)
	1239	void helper_mtc0_cause (target_ulong t0)
1230	1240	{
1231	1241	uint32_t mask = 0x00C00300;
1232	1242	uint32_t old = env->CP0_Cause;
...	...
1250	1260	}
1251	1261	}
1252	1262
1253		void do_mtc0_ebase (target_ulong t0)
	1263	void helper_mtc0_ebase (target_ulong t0)
1254	1264	{
1255	1265	/* vectored interrupts not implemented */
1256	1266	/* Multi-CPU not implemented */
1257	1267	env->CP0_EBase = 0x80000000 \| (t0 & 0x3FFFF000);
1258	1268	}
1259	1269
1260		void do_mtc0_config0 (target_ulong t0)
	1270	void helper_mtc0_config0 (target_ulong t0)
1261	1271	{
1262	1272	env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) \| (t0 & 0x00000007);
1263	1273	}
1264	1274
1265		void do_mtc0_config2 (target_ulong t0)
	1275	void helper_mtc0_config2 (target_ulong t0)
1266	1276	{
1267	1277	/* tertiary/secondary caches not implemented */
1268	1278	env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1269	1279	}
1270	1280
1271		void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
	1281	void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
1272	1282	{
1273	1283	/* Watch exceptions for instructions, data loads, data stores
1274	1284	not implemented. */
1275	1285	env->CP0_WatchLo[sel] = (t0 & ~0x7);
1276	1286	}
1277	1287
1278		void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
	1288	void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
1279	1289	{
1280	1290	env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1281	1291	env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
1282	1292	}
1283	1293
1284		void do_mtc0_xcontext (target_ulong t0)
	1294	void helper_mtc0_xcontext (target_ulong t0)
1285	1295	{
1286	1296	target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1287	1297	env->CP0_XContext = (env->CP0_XContext & mask) \| (t0 & ~mask);
1288	1298	}
1289	1299
1290		void do_mtc0_framemask (target_ulong t0)
	1300	void helper_mtc0_framemask (target_ulong t0)
1291	1301	{
1292	1302	env->CP0_Framemask = t0; /* XXX */
1293	1303	}
1294	1304
1295		void do_mtc0_debug (target_ulong t0)
	1305	void helper_mtc0_debug (target_ulong t0)
1296	1306	{
1297	1307	env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) \| (t0 & 0x13300120);
1298	1308	if (t0 & (1 << CP0DB_DM))
...	...
1301	1311	env->hflags &= ~MIPS_HFLAG_DM;
1302	1312	}
1303	1313
1304		void do_mttc0_debug(target_ulong t0)
	1314	void helper_mttc0_debug(target_ulong t0)
1305	1315	{
1306	1316	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1307	1317	uint32_t val = t0 & ((1 << CP0DB_SSt) \| (1 << CP0DB_Halt));
...	...
1315	1325	(t0 & ~((1 << CP0DB_SSt) \| (1 << CP0DB_Halt)));
1316	1326	}
1317	1327
1318		void do_mtc0_performance0 (target_ulong t0)
	1328	void helper_mtc0_performance0 (target_ulong t0)
1319	1329	{
1320	1330	env->CP0_Performance0 = t0 & 0x000007ff;
1321	1331	}
1322	1332
1323		void do_mtc0_taglo (target_ulong t0)
	1333	void helper_mtc0_taglo (target_ulong t0)
1324	1334	{
1325	1335	env->CP0_TagLo = t0 & 0xFFFFFCF6;
1326	1336	}
1327	1337
1328		void do_mtc0_datalo (target_ulong t0)
	1338	void helper_mtc0_datalo (target_ulong t0)
1329	1339	{
1330	1340	env->CP0_DataLo = t0; /* XXX */
1331	1341	}
1332	1342
1333		void do_mtc0_taghi (target_ulong t0)
	1343	void helper_mtc0_taghi (target_ulong t0)
1334	1344	{
1335	1345	env->CP0_TagHi = t0; /* XXX */
1336	1346	}
1337	1347
1338		void do_mtc0_datahi (target_ulong t0)
	1348	void helper_mtc0_datahi (target_ulong t0)
1339	1349	{
1340	1350	env->CP0_DataHi = t0; /* XXX */
1341	1351	}
1342	1352
1343		void do_mtc0_status_debug(uint32_t old, uint32_t val)
1344		{
1345		qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1346		old, old & env->CP0_Cause & CP0Ca_IP_mask,
1347		val, val & env->CP0_Cause & CP0Ca_IP_mask,
1348		env->CP0_Cause);
1349		switch (env->hflags & MIPS_HFLAG_KSU) {
1350		case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1351		case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1352		case MIPS_HFLAG_KM: qemu_log("\n"); break;
1353		default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1354		}
1355		}
1356
1357		void do_mtc0_status_irqraise_debug(void)
1358		{
1359		qemu_log("Raise pending IRQs\n");
1360		}
1361
1362	1353	/* MIPS MT functions */
1363		target_ulong do_mftgpr(uint32_t sel)
	1354	target_ulong helper_mftgpr(uint32_t sel)
1364	1355	{
1365	1356	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1366	1357
...	...
1370	1361	return env->tcs[other_tc].gpr[sel];
1371	1362	}
1372	1363
1373		target_ulong do_mftlo(uint32_t sel)
	1364	target_ulong helper_mftlo(uint32_t sel)
1374	1365	{
1375	1366	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376	1367
...	...
1380	1371	return env->tcs[other_tc].LO[sel];
1381	1372	}
1382	1373
1383		target_ulong do_mfthi(uint32_t sel)
	1374	target_ulong helper_mfthi(uint32_t sel)
1384	1375	{
1385	1376	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1386	1377
...	...
1390	1381	return env->tcs[other_tc].HI[sel];
1391	1382	}
1392	1383
1393		target_ulong do_mftacx(uint32_t sel)
	1384	target_ulong helper_mftacx(uint32_t sel)
1394	1385	{
1395	1386	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1396	1387
...	...
1400	1391	return env->tcs[other_tc].ACX[sel];
1401	1392	}
1402	1393
1403		target_ulong do_mftdsp(void)
	1394	target_ulong helper_mftdsp(void)
1404	1395	{
1405	1396	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1406	1397
...	...
1410	1401	return env->tcs[other_tc].DSPControl;
1411	1402	}
1412	1403
1413		void do_mttgpr(target_ulong t0, uint32_t sel)
	1404	void helper_mttgpr(target_ulong t0, uint32_t sel)
1414	1405	{
1415	1406	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1416	1407
...	...
1420	1411	env->tcs[other_tc].gpr[sel] = t0;
1421	1412	}
1422	1413
1423		void do_mttlo(target_ulong t0, uint32_t sel)
	1414	void helper_mttlo(target_ulong t0, uint32_t sel)
1424	1415	{
1425	1416	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426	1417
...	...
1430	1421	env->tcs[other_tc].LO[sel] = t0;
1431	1422	}
1432	1423
1433		void do_mtthi(target_ulong t0, uint32_t sel)
	1424	void helper_mtthi(target_ulong t0, uint32_t sel)
1434	1425	{
1435	1426	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1436	1427
...	...
1440	1431	env->tcs[other_tc].HI[sel] = t0;
1441	1432	}
1442	1433
1443		void do_mttacx(target_ulong t0, uint32_t sel)
	1434	void helper_mttacx(target_ulong t0, uint32_t sel)
1444	1435	{
1445	1436	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1446	1437
...	...
1450	1441	env->tcs[other_tc].ACX[sel] = t0;
1451	1442	}
1452	1443
1453		void do_mttdsp(target_ulong t0)
	1444	void helper_mttdsp(target_ulong t0)
1454	1445	{
1455	1446	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1456	1447
...	...
1461	1452	}
1462	1453
1463	1454	/* MIPS MT functions */
1464		target_ulong do_dmt(target_ulong t0)
	1455	target_ulong helper_dmt(target_ulong t0)
1465	1456	{
1466	1457	// TODO
1467	1458	t0 = 0;
...	...
1470	1461	return t0;
1471	1462	}
1472	1463
1473		target_ulong do_emt(target_ulong t0)
	1464	target_ulong helper_emt(target_ulong t0)
1474	1465	{
1475	1466	// TODO
1476	1467	t0 = 0;
...	...
1479	1470	return t0;
1480	1471	}
1481	1472
1482		target_ulong do_dvpe(target_ulong t0)
	1473	target_ulong helper_dvpe(target_ulong t0)
1483	1474	{
1484	1475	// TODO
1485	1476	t0 = 0;
...	...
1488	1479	return t0;
1489	1480	}
1490	1481
1491		target_ulong do_evpe(target_ulong t0)
	1482	target_ulong helper_evpe(target_ulong t0)
1492	1483	{
1493	1484	// TODO
1494	1485	t0 = 0;
...	...
1498	1489	}
1499	1490	#endif /* !CONFIG_USER_ONLY */
1500	1491
1501		void do_fork(target_ulong t0, target_ulong t1)
	1492	void helper_fork(target_ulong t0, target_ulong t1)
1502	1493	{
1503	1494	// t0 = rt, t1 = rs
1504	1495	t0 = 0;
1505	1496	// TODO: store to TC register
1506	1497	}
1507	1498
1508		target_ulong do_yield(target_ulong t0)
	1499	target_ulong helper_yield(target_ulong t0)
1509	1500	{
1510	1501	if (t0 < 0) {
1511	1502	/* No scheduling policy implemented. */
...	...
1514	1505	env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1515	1506	env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1516	1507	env->CP0_VPEControl \|= 4 << CP0VPECo_EXCPT;
1517		do_raise_exception(EXCP_THREAD);
	1508	helper_raise_exception(EXCP_THREAD);
1518	1509	}
1519	1510	}
1520	1511	} else if (t0 == 0) {
1521	1512	if (0 /* TODO: TC underflow */) {
1522	1513	env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1523		do_raise_exception(EXCP_THREAD);
	1514	helper_raise_exception(EXCP_THREAD);
1524	1515	} else {
1525	1516	// TODO: Deallocate TC
1526	1517	}
...	...
1528	1519	/* Yield qualifier inputs not implemented. */
1529	1520	env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1530	1521	env->CP0_VPEControl \|= 2 << CP0VPECo_EXCPT;
1531		do_raise_exception(EXCP_THREAD);
	1522	helper_raise_exception(EXCP_THREAD);
1532	1523	}
1533	1524	return env->CP0_YQMask;
1534	1525	}
...	...
1573	1564	tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1574	1565	}
1575	1566
1576		void r4k_do_tlbwi (void)
	1567	void r4k_helper_tlbwi (void)
1577	1568	{
1578	1569	int idx;
1579	1570
...	...
1588	1579	r4k_fill_tlb(idx);
1589	1580	}
1590	1581
1591		void r4k_do_tlbwr (void)
	1582	void r4k_helper_tlbwr (void)
1592	1583	{
1593	1584	int r = cpu_mips_get_random(env);
1594	1585
...	...
1596	1587	r4k_fill_tlb(r);
1597	1588	}
1598	1589
1599		void r4k_do_tlbp (void)
	1590	void r4k_helper_tlbp (void)
1600	1591	{
1601	1592	r4k_tlb_t *tlb;
1602	1593	target_ulong mask;
...	...
1638	1629	}
1639	1630	}
1640	1631
1641		void r4k_do_tlbr (void)
	1632	void r4k_helper_tlbr (void)
1642	1633	{
1643	1634	r4k_tlb_t *tlb;
1644	1635	uint8_t ASID;
...	...
1662	1653	(tlb->C1 << 3) \| (tlb->PFN[1] >> 6);
1663	1654	}
1664	1655
1665		void do_tlbwi(void)
	1656	void helper_tlbwi(void)
1666	1657	{
1667		env->tlb->do_tlbwi();
	1658	env->tlb->helper_tlbwi();
1668	1659	}
1669	1660
1670		void do_tlbwr(void)
	1661	void helper_tlbwr(void)
1671	1662	{
1672		env->tlb->do_tlbwr();
	1663	env->tlb->helper_tlbwr();
1673	1664	}
1674	1665
1675		void do_tlbp(void)
	1666	void helper_tlbp(void)
1676	1667	{
1677		env->tlb->do_tlbp();
	1668	env->tlb->helper_tlbp();
1678	1669	}
1679	1670
1680		void do_tlbr(void)
	1671	void helper_tlbr(void)
1681	1672	{
1682		env->tlb->do_tlbr();
	1673	env->tlb->helper_tlbr();
1683	1674	}
1684	1675
1685	1676	/* Specials */
1686		target_ulong do_di (void)
	1677	target_ulong helper_di (void)
1687	1678	{
1688	1679	target_ulong t0 = env->CP0_Status;
1689	1680
...	...
1693	1684	return t0;
1694	1685	}
1695	1686
1696		target_ulong do_ei (void)
	1687	target_ulong helper_ei (void)
1697	1688	{
1698	1689	target_ulong t0 = env->CP0_Status;
1699	1690
...	...
1734	1725	}
1735	1726	}
1736	1727
1737		void do_eret (void)
	1728	void helper_eret (void)
1738	1729	{
1739	1730	debug_pre_eret();
1740	1731	if (env->CP0_Status & (1 << CP0St_ERL)) {
...	...
1749	1740	env->CP0_LLAddr = 1;
1750	1741	}
1751	1742
1752		void do_deret (void)
	1743	void helper_deret (void)
1753	1744	{
1754	1745	debug_pre_eret();
1755	1746	env->active_tc.PC = env->CP0_DEPC;
...	...
1760	1751	}
1761	1752	#endif /* !CONFIG_USER_ONLY */
1762	1753
1763		target_ulong do_rdhwr_cpunum(void)
	1754	target_ulong helper_rdhwr_cpunum(void)
1764	1755	{
1765	1756	if ((env->hflags & MIPS_HFLAG_CP0) \|\|
1766	1757	(env->CP0_HWREna & (1 << 0)))
1767	1758	return env->CP0_EBase & 0x3ff;
1768	1759	else
1769		do_raise_exception(EXCP_RI);
	1760	helper_raise_exception(EXCP_RI);
1770	1761
1771	1762	return 0;
1772	1763	}
1773	1764
1774		target_ulong do_rdhwr_synci_step(void)
	1765	target_ulong helper_rdhwr_synci_step(void)
1775	1766	{
1776	1767	if ((env->hflags & MIPS_HFLAG_CP0) \|\|
1777	1768	(env->CP0_HWREna & (1 << 1)))
1778	1769	return env->SYNCI_Step;
1779	1770	else
1780		do_raise_exception(EXCP_RI);
	1771	helper_raise_exception(EXCP_RI);
1781	1772
1782	1773	return 0;
1783	1774	}
1784	1775
1785		target_ulong do_rdhwr_cc(void)
	1776	target_ulong helper_rdhwr_cc(void)
1786	1777	{
1787	1778	if ((env->hflags & MIPS_HFLAG_CP0) \|\|
1788	1779	(env->CP0_HWREna & (1 << 2)))
1789	1780	return env->CP0_Count;
1790	1781	else
1791		do_raise_exception(EXCP_RI);
	1782	helper_raise_exception(EXCP_RI);
1792	1783
1793	1784	return 0;
1794	1785	}
1795	1786
1796		target_ulong do_rdhwr_ccres(void)
	1787	target_ulong helper_rdhwr_ccres(void)
1797	1788	{
1798	1789	if ((env->hflags & MIPS_HFLAG_CP0) \|\|
1799	1790	(env->CP0_HWREna & (1 << 3)))
1800	1791	return env->CCRes;
1801	1792	else
1802		do_raise_exception(EXCP_RI);
	1793	helper_raise_exception(EXCP_RI);
1803	1794
1804	1795	return 0;
1805	1796	}
1806	1797
1807		void do_pmon (int function)
	1798	void helper_pmon (int function)
1808	1799	{
1809	1800	function /= 2;
1810	1801	switch (function) {
...	...
1830	1821	}
1831	1822	}
1832	1823
1833		void do_wait (void)
	1824	void helper_wait (void)
1834	1825	{
1835	1826	env->halted = 1;
1836		do_raise_exception(EXCP_HLT);
	1827	helper_raise_exception(EXCP_HLT);
1837	1828	}
1838	1829
1839	1830	#if !defined(CONFIG_USER_ONLY)
...	...
1859	1850	{
1860	1851	env->CP0_BadVAddr = addr;
1861	1852	do_restore_state (retaddr);
1862		do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
	1853	helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1863	1854	}
1864	1855
1865	1856	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
...	...
1885	1876	cpu_restore_state(tb, env, pc, NULL);
1886	1877	}
1887	1878	}
1888		do_raise_exception_err(env->exception_index, env->error_code);
	1879	helper_raise_exception_err(env->exception_index, env->error_code);
1889	1880	}
1890	1881	env = saved_env;
1891	1882	}
...	...
1894	1885	int unused, int size)
1895	1886	{
1896	1887	if (is_exec)
1897		do_raise_exception(EXCP_IBE);
	1888	helper_raise_exception(EXCP_IBE);
1898	1889	else
1899		do_raise_exception(EXCP_DBE);
	1890	helper_raise_exception(EXCP_DBE);
1900	1891	}
1901	1892	#endif /* !CONFIG_USER_ONLY */
1902	1893
...	...
1922	1913	#define RESTORE_ROUNDING_MODE \
1923	1914	set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1924	1915
1925		target_ulong do_cfc1 (uint32_t reg)
	1916	target_ulong helper_cfc1 (uint32_t reg)
1926	1917	{
1927	1918	target_ulong t0;
1928	1919
...	...
1947	1938	return t0;
1948	1939	}
1949	1940
1950		void do_ctc1 (target_ulong t0, uint32_t reg)
	1941	void helper_ctc1 (target_ulong t0, uint32_t reg)
1951	1942	{
1952	1943	switch(reg) {
1953	1944	case 25:
...	...
1979	1970	RESTORE_ROUNDING_MODE;
1980	1971	set_float_exception_flags(0, &env->active_fpu.fp_status);
1981	1972	if ((GET_FP_ENABLE(env->active_fpu.fcr31) \| 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
1982		do_raise_exception(EXCP_FPE);
	1973	helper_raise_exception(EXCP_FPE);
1983	1974	}
1984	1975
1985	1976	static inline char ieee_ex_to_mips(char xcpt)
...	...
2006	1997
2007	1998	SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2008	1999	if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2009		do_raise_exception(EXCP_FPE);
	2000	helper_raise_exception(EXCP_FPE);
2010	2001	else
2011	2002	UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2012	2003	}
...	...
2017	2008	paired single lower "pl", paired single upper "pu". */
2018	2009
2019	2010	/* unary operations, modifying fp status */
2020		uint64_t do_float_sqrt_d(uint64_t fdt0)
	2011	uint64_t helper_float_sqrt_d(uint64_t fdt0)
2021	2012	{
2022	2013	return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2023	2014	}
2024	2015
2025		uint32_t do_float_sqrt_s(uint32_t fst0)
	2016	uint32_t helper_float_sqrt_s(uint32_t fst0)
2026	2017	{
2027	2018	return float32_sqrt(fst0, &env->active_fpu.fp_status);
2028	2019	}
2029	2020
2030		uint64_t do_float_cvtd_s(uint32_t fst0)
	2021	uint64_t helper_float_cvtd_s(uint32_t fst0)
2031	2022	{
2032	2023	uint64_t fdt2;
2033	2024
...	...
2037	2028	return fdt2;
2038	2029	}
2039	2030
2040		uint64_t do_float_cvtd_w(uint32_t wt0)
	2031	uint64_t helper_float_cvtd_w(uint32_t wt0)

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Archipelago » qemu

Revision c01fccd2