Revision c047da1a target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 1226 | 1226 |
return; |
| 1227 | 1227 |
case 0x4000: /* shll Rn */ |
| 1228 | 1228 |
case 0x4020: /* shal Rn */ |
| 1229 |
gen_op_shal_Rn(REG(B11_8)); |
|
| 1229 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000); |
|
| 1230 |
gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); |
|
| 1231 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1230 | 1232 |
return; |
| 1231 | 1233 |
case 0x4021: /* shar Rn */ |
| 1232 |
gen_op_shar_Rn(REG(B11_8)); |
|
| 1234 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); |
|
| 1235 |
gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); |
|
| 1236 |
tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1233 | 1237 |
return; |
| 1234 | 1238 |
case 0x4001: /* shlr Rn */ |
| 1235 |
gen_op_shlr_Rn(REG(B11_8)); |
|
| 1239 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); |
|
| 1240 |
gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); |
|
| 1241 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1236 | 1242 |
return; |
| 1237 | 1243 |
case 0x4008: /* shll2 Rn */ |
| 1238 | 1244 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2); |
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