Revision c0532a76 target-i386/cpu.h
| b/target-i386/cpu.h | ||
|---|---|---|
| 250 | 250 |
#define PG_ERROR_RSVD_MASK 0x08 |
| 251 | 251 |
#define PG_ERROR_I_D_MASK 0x10 |
| 252 | 252 |
|
| 253 |
#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ |
|
| 253 |
#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
|
| 254 |
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
|
| 254 | 255 |
|
| 255 |
#define MCE_CAP_DEF MCG_CTL_P
|
|
| 256 |
#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
|
|
| 256 | 257 |
#define MCE_BANKS_DEF 10 |
| 257 | 258 |
|
| 259 |
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
|
| 260 |
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
|
| 258 | 261 |
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
| 259 | 262 |
|
| 260 | 263 |
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| 261 | 264 |
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| 262 | 265 |
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
| 266 |
#define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
|
| 267 |
#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
|
| 268 |
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
|
| 269 |
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
|
| 270 |
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
|
| 271 |
#define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
|
| 272 |
|
|
| 273 |
/* MISC register defines */ |
|
| 274 |
#define MCM_ADDR_SEGOFF 0 /* segment offset */ |
|
| 275 |
#define MCM_ADDR_LINEAR 1 /* linear address */ |
|
| 276 |
#define MCM_ADDR_PHYS 2 /* physical address */ |
|
| 277 |
#define MCM_ADDR_MEM 3 /* memory address */ |
|
| 278 |
#define MCM_ADDR_GENERIC 7 /* generic */ |
|
| 263 | 279 |
|
| 264 | 280 |
#define MSR_IA32_TSC 0x10 |
| 265 | 281 |
#define MSR_IA32_APICBASE 0x1b |
Also available in: Unified diff