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/*
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 * i386 virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#define TARGET_HAS_ICE 1
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#ifdef TARGET_X86_64
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#define ELF_MACHINE        EM_X86_64
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#else
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#define ELF_MACHINE        EM_386
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#endif
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#define CPUState struct CPUX86State
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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/* hidden flags - used internally by qemu to represent additional cpu
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   states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
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   redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
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   position to ease oring with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_RF_SHIFT         16 /* must be same as eflags */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
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#define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
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#define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_RF_MASK           (1 << HF_RF_SHIFT)
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#define HF_VM_MASK           (1 << HF_VM_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
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#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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/* hflags2 */
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#define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
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#define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
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#define HF2_NMI_SHIFT        2 /* CPU serving NMI */
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#define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
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#define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
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#define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT) 
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#define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
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#define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
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#define CR0_PE_SHIFT 0
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#define CR0_MP_SHIFT 1
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_MCE_MASK  (1 << 6)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_SHIFT 9
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#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define DR6_BD          (1 << 13)
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#define DR6_BS          (1 << 14)
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#define DR6_BT          (1 << 15)
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#define DR6_FIXED_1     0xffff0ff0
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#define DR7_GD          (1 << 13)
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#define DR7_TYPE_SHIFT  16
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#define DR7_LEN_SHIFT   18
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#define DR7_FIXED_1     0x00000400
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#define PG_PRESENT_BIT        0
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#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_NX_BIT        63
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_NX_MASK         (1LL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1
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#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define PG_ERROR_I_D_MASK  0x10
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#define MCG_CTL_P        (1ULL<<8)   /* MCG_CAP register available */
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#define MCG_SER_P        (1ULL<<24) /* MCA recovery/new status bits */
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#define MCE_CAP_DEF        (MCG_CTL_P|MCG_SER_P)
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#define MCE_BANKS_DEF        10
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#define MCG_STATUS_RIPV        (1ULL<<0)   /* restart ip valid */
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#define MCG_STATUS_EIPV        (1ULL<<1)   /* ip points to correct instruction */
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#define MCG_STATUS_MCIP        (1ULL<<2)   /* machine check in progress */
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#define MCI_STATUS_VAL        (1ULL<<63)  /* valid error */
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#define MCI_STATUS_OVER        (1ULL<<62)  /* previous errors lost */
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#define MCI_STATUS_UC        (1ULL<<61)  /* uncorrected error */
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#define MCI_STATUS_EN        (1ULL<<60)  /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC        (1ULL<<57)  /* processor context corrupt */
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#define MCI_STATUS_S        (1ULL<<56)  /* Signaled machine check */
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#define MCI_STATUS_AR        (1ULL<<55)  /* Action required */
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/* MISC register defines */
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#define MCM_ADDR_SEGOFF        0        /* segment offset */
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#define MCM_ADDR_LINEAR        1        /* linear address */
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#define MCM_ADDR_PHYS        2        /* physical address */
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#define MCM_ADDR_MEM        3        /* memory address */
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#define MCM_ADDR_GENERIC 7        /* generic */
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#define MSR_IA32_TSC                    0x10
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#define MSR_IA32_APICBASE               0x1b
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#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_MTRRcap                        0xfe
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#define MSR_MTRRcap_VCNT                8
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#define MSR_MTRRcap_FIXRANGE_SUPPORT        (1 << 8)
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#define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_MCG_CAP                     0x179
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#define MSR_MCG_STATUS                  0x17a
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#define MSR_MCG_CTL                     0x17b
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#define MSR_IA32_PERF_STATUS            0x198
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#define MSR_MTRRphysBase(reg)                (0x200 + 2 * (reg))
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#define MSR_MTRRphysMask(reg)                (0x200 + 2 * (reg) + 1)
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#define MSR_MTRRfix64K_00000                0x250
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#define MSR_MTRRfix16K_80000                0x258
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#define MSR_MTRRfix16K_A0000                0x259
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#define MSR_MTRRfix4K_C0000                0x268
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#define MSR_MTRRfix4K_C8000                0x269
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#define MSR_MTRRfix4K_D0000                0x26a
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#define MSR_MTRRfix4K_D8000                0x26b
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#define MSR_MTRRfix4K_E0000                0x26c
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#define MSR_MTRRfix4K_E8000                0x26d
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#define MSR_MTRRfix4K_F0000                0x26e
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#define MSR_MTRRfix4K_F8000                0x26f
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#define MSR_PAT                         0x277
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#define MSR_MTRRdefType                        0x2ff
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#define MSR_MC0_CTL                        0x400
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#define MSR_MC0_STATUS                        0x401
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#define MSR_MC0_ADDR                        0x402
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#define MSR_MC0_MISC                        0x403
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#define MSR_EFER                        0xc0000080
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_SVME  (1 << 12)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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#define MSR_TSC_AUX                     0xc0000103
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#define MSR_VM_HSAVE_PA                 0xc0010117
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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#define CPUID_PAT  (1 << 16)
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#define CPUID_PSE36   (1 << 17)
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#define CPUID_PN   (1 << 18)
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#define CPUID_CLFLUSH (1 << 19)
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#define CPUID_DTS (1 << 21)
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#define CPUID_ACPI (1 << 22)
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define CPUID_SS (1 << 27)
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#define CPUID_HT (1 << 28)
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#define CPUID_TM (1 << 29)
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#define CPUID_IA64 (1 << 30)
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#define CPUID_PBE (1 << 31)
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#define CPUID_EXT_SSE3     (1 << 0)
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#define CPUID_EXT_DTES64   (1 << 2)
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#define CPUID_EXT_MONITOR  (1 << 3)
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#define CPUID_EXT_DSCPL    (1 << 4)
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#define CPUID_EXT_VMX      (1 << 5)
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#define CPUID_EXT_SMX      (1 << 6)
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#define CPUID_EXT_EST      (1 << 7)
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#define CPUID_EXT_TM2      (1 << 8)
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#define CPUID_EXT_SSSE3    (1 << 9)
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#define CPUID_EXT_CID      (1 << 10)
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#define CPUID_EXT_CX16     (1 << 13)
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#define CPUID_EXT_XTPR     (1 << 14)
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#define CPUID_EXT_PDCM     (1 << 15)
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#define CPUID_EXT_DCA      (1 << 18)
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#define CPUID_EXT_SSE41    (1 << 19)
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#define CPUID_EXT_SSE42    (1 << 20)
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#define CPUID_EXT_X2APIC   (1 << 21)
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#define CPUID_EXT_MOVBE    (1 << 22)
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#define CPUID_EXT_POPCNT   (1 << 23)
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#define CPUID_EXT_XSAVE    (1 << 26)
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#define CPUID_EXT_OSXSAVE  (1 << 27)
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#define CPUID_EXT_HYPERVISOR  (1 << 31)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_MP      (1 << 19)
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#define CPUID_EXT2_NX      (1 << 20)
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#define CPUID_EXT2_MMXEXT  (1 << 22)
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#define CPUID_EXT2_FFXSR   (1 << 25)
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#define CPUID_EXT2_PDPE1GB (1 << 26)
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#define CPUID_EXT2_RDTSCP  (1 << 27)
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#define CPUID_EXT2_LM      (1 << 29)
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#define CPUID_EXT2_3DNOWEXT (1 << 30)
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#define CPUID_EXT2_3DNOW   (1 << 31)
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#define CPUID_EXT3_LAHF_LM (1 << 0)
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#define CPUID_EXT3_CMP_LEG (1 << 1)
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#define CPUID_EXT3_SVM     (1 << 2)
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#define CPUID_EXT3_EXTAPIC (1 << 3)
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#define CPUID_EXT3_CR8LEG  (1 << 4)
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#define CPUID_EXT3_ABM     (1 << 5)
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#define CPUID_EXT3_SSE4A   (1 << 6)
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#define CPUID_EXT3_MISALIGNSSE (1 << 7)
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#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
420
#define CPUID_EXT3_OSVW    (1 << 9)
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#define CPUID_EXT3_IBS     (1 << 10)
422
#define CPUID_EXT3_SKINIT  (1 << 12)
423

    
424
#define CPUID_SVM_NPT          (1 << 0)
425
#define CPUID_SVM_LBRV         (1 << 1)
426
#define CPUID_SVM_SVMLOCK      (1 << 2)
427
#define CPUID_SVM_NRIPSAVE     (1 << 3)
428
#define CPUID_SVM_TSCSCALE     (1 << 4)
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#define CPUID_SVM_VMCBCLEAN    (1 << 5)
430
#define CPUID_SVM_FLUSHASID    (1 << 6)
431
#define CPUID_SVM_DECODEASSIST (1 << 7)
432
#define CPUID_SVM_PAUSEFILTER  (1 << 10)
433
#define CPUID_SVM_PFTHRESHOLD  (1 << 12)
434

    
435
#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
436
#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
437
#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
438

    
439
#define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
440
#define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */ 
441
#define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
442

    
443
#define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
444
#define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
445

    
446
#define EXCP00_DIVZ        0
447
#define EXCP01_DB        1
448
#define EXCP02_NMI        2
449
#define EXCP03_INT3        3
450
#define EXCP04_INTO        4
451
#define EXCP05_BOUND        5
452
#define EXCP06_ILLOP        6
453
#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
455
#define EXCP09_XERR        9
456
#define EXCP0A_TSS        10
457
#define EXCP0B_NOSEG        11
458
#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
460
#define EXCP0E_PAGE        14
461
#define EXCP10_COPR        16
462
#define EXCP11_ALGN        17
463
#define EXCP12_MCHK        18
464

    
465
#define EXCP_SYSCALL    0x100 /* only happens in user only emulation
466
                                 for syscall instruction */
467

    
468
enum {
469
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
470
    CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
471

    
472
    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
473
    CC_OP_MULW,
474
    CC_OP_MULL,
475
    CC_OP_MULQ,
476

    
477
    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
478
    CC_OP_ADDW,
479
    CC_OP_ADDL,
480
    CC_OP_ADDQ,
481

    
482
    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
483
    CC_OP_ADCW,
484
    CC_OP_ADCL,
485
    CC_OP_ADCQ,
486

    
487
    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
488
    CC_OP_SUBW,
489
    CC_OP_SUBL,
490
    CC_OP_SUBQ,
491

    
492
    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
493
    CC_OP_SBBW,
494
    CC_OP_SBBL,
495
    CC_OP_SBBQ,
496

    
497
    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
498
    CC_OP_LOGICW,
499
    CC_OP_LOGICL,
500
    CC_OP_LOGICQ,
501

    
502
    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
503
    CC_OP_INCW,
504
    CC_OP_INCL,
505
    CC_OP_INCQ,
506

    
507
    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
508
    CC_OP_DECW,
509
    CC_OP_DECL,
510
    CC_OP_DECQ,
511

    
512
    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
513
    CC_OP_SHLW,
514
    CC_OP_SHLL,
515
    CC_OP_SHLQ,
516

    
517
    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
518
    CC_OP_SARW,
519
    CC_OP_SARL,
520
    CC_OP_SARQ,
521

    
522
    CC_OP_NB,
523
};
524

    
525
#ifdef FLOATX80
526
#define USE_X86LDOUBLE
527
#endif
528

    
529
#ifdef USE_X86LDOUBLE
530
typedef floatx80 CPU86_LDouble;
531
#else
532
typedef float64 CPU86_LDouble;
533
#endif
534

    
535
typedef struct SegmentCache {
536
    uint32_t selector;
537
    target_ulong base;
538
    uint32_t limit;
539
    uint32_t flags;
540
} SegmentCache;
541

    
542
typedef union {
543
    uint8_t _b[16];
544
    uint16_t _w[8];
545
    uint32_t _l[4];
546
    uint64_t _q[2];
547
    float32 _s[4];
548
    float64 _d[2];
549
} XMMReg;
550

    
551
typedef union {
552
    uint8_t _b[8];
553
    uint16_t _w[4];
554
    uint32_t _l[2];
555
    float32 _s[2];
556
    uint64_t q;
557
} MMXReg;
558

    
559
#ifdef HOST_WORDS_BIGENDIAN
560
#define XMM_B(n) _b[15 - (n)]
561
#define XMM_W(n) _w[7 - (n)]
562
#define XMM_L(n) _l[3 - (n)]
563
#define XMM_S(n) _s[3 - (n)]
564
#define XMM_Q(n) _q[1 - (n)]
565
#define XMM_D(n) _d[1 - (n)]
566

    
567
#define MMX_B(n) _b[7 - (n)]
568
#define MMX_W(n) _w[3 - (n)]
569
#define MMX_L(n) _l[1 - (n)]
570
#define MMX_S(n) _s[1 - (n)]
571
#else
572
#define XMM_B(n) _b[n]
573
#define XMM_W(n) _w[n]
574
#define XMM_L(n) _l[n]
575
#define XMM_S(n) _s[n]
576
#define XMM_Q(n) _q[n]
577
#define XMM_D(n) _d[n]
578

    
579
#define MMX_B(n) _b[n]
580
#define MMX_W(n) _w[n]
581
#define MMX_L(n) _l[n]
582
#define MMX_S(n) _s[n]
583
#endif
584
#define MMX_Q(n) q
585

    
586
typedef union {
587
#ifdef USE_X86LDOUBLE
588
    CPU86_LDouble d __attribute__((aligned(16)));
589
#else
590
    CPU86_LDouble d;
591
#endif
592
    MMXReg mmx;
593
} FPReg;
594

    
595
typedef struct {
596
    uint64_t base;
597
    uint64_t mask;
598
} MTRRVar;
599

    
600
#define CPU_NB_REGS64 16
601
#define CPU_NB_REGS32 8
602

    
603
#ifdef TARGET_X86_64
604
#define CPU_NB_REGS CPU_NB_REGS64
605
#else
606
#define CPU_NB_REGS CPU_NB_REGS32
607
#endif
608

    
609
#define NB_MMU_MODES 2
610

    
611
typedef struct CPUX86State {
612
    /* standard registers */
613
    target_ulong regs[CPU_NB_REGS];
614
    target_ulong eip;
615
    target_ulong eflags; /* eflags register. During CPU emulation, CC
616
                        flags and DF are set to zero because they are
617
                        stored elsewhere */
618

    
619
    /* emulator internal eflags handling */
620
    target_ulong cc_src;
621
    target_ulong cc_dst;
622
    uint32_t cc_op;
623
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
624
    uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
625
                        are known at translation time. */
626
    uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
627

    
628
    /* segments */
629
    SegmentCache segs[6]; /* selector values */
630
    SegmentCache ldt;
631
    SegmentCache tr;
632
    SegmentCache gdt; /* only base and limit are used */
633
    SegmentCache idt; /* only base and limit are used */
634

    
635
    target_ulong cr[5]; /* NOTE: cr1 is unused */
636
    int32_t a20_mask;
637

    
638
    /* FPU state */
639
    unsigned int fpstt; /* top of stack index */
640
    uint16_t fpus;
641
    uint16_t fpuc;
642
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
643
    FPReg fpregs[8];
644

    
645
    /* emulator internal variables */
646
    float_status fp_status;
647
    CPU86_LDouble ft0;
648

    
649
    float_status mmx_status; /* for 3DNow! float ops */
650
    float_status sse_status;
651
    uint32_t mxcsr;
652
    XMMReg xmm_regs[CPU_NB_REGS];
653
    XMMReg xmm_t0;
654
    MMXReg mmx_t0;
655
    target_ulong cc_tmp; /* temporary for rcr/rcl */
656

    
657
    /* sysenter registers */
658
    uint32_t sysenter_cs;
659
    target_ulong sysenter_esp;
660
    target_ulong sysenter_eip;
661
    uint64_t efer;
662
    uint64_t star;
663

    
664
    uint64_t vm_hsave;
665
    uint64_t vm_vmcb;
666
    uint64_t tsc_offset;
667
    uint64_t intercept;
668
    uint16_t intercept_cr_read;
669
    uint16_t intercept_cr_write;
670
    uint16_t intercept_dr_read;
671
    uint16_t intercept_dr_write;
672
    uint32_t intercept_exceptions;
673
    uint8_t v_tpr;
674

    
675
#ifdef TARGET_X86_64
676
    target_ulong lstar;
677
    target_ulong cstar;
678
    target_ulong fmask;
679
    target_ulong kernelgsbase;
680
#endif
681
    uint64_t system_time_msr;
682
    uint64_t wall_clock_msr;
683

    
684
    uint64_t tsc;
685

    
686
    uint64_t pat;
687

    
688
    /* exception/interrupt handling */
689
    int error_code;
690
    int exception_is_int;
691
    target_ulong exception_next_eip;
692
    target_ulong dr[8]; /* debug registers */
693
    union {
694
        CPUBreakpoint *cpu_breakpoint[4];
695
        CPUWatchpoint *cpu_watchpoint[4];
696
    }; /* break/watchpoints for dr[0..3] */
697
    uint32_t smbase;
698
    int old_exception;  /* exception in flight */
699

    
700
    CPU_COMMON
701

    
702
    /* processor features (e.g. for CPUID insn) */
703
    uint32_t cpuid_level;
704
    uint32_t cpuid_vendor1;
705
    uint32_t cpuid_vendor2;
706
    uint32_t cpuid_vendor3;
707
    uint32_t cpuid_version;
708
    uint32_t cpuid_features;
709
    uint32_t cpuid_ext_features;
710
    uint32_t cpuid_xlevel;
711
    uint32_t cpuid_model[12];
712
    uint32_t cpuid_ext2_features;
713
    uint32_t cpuid_ext3_features;
714
    uint32_t cpuid_apic_id;
715
    int cpuid_vendor_override;
716

    
717
    /* MTRRs */
718
    uint64_t mtrr_fixed[11];
719
    uint64_t mtrr_deftype;
720
    MTRRVar mtrr_var[8];
721

    
722
    /* For KVM */
723
    uint32_t mp_state;
724
    int32_t exception_injected;
725
    int32_t interrupt_injected;
726
    uint8_t soft_interrupt;
727
    uint8_t nmi_injected;
728
    uint8_t nmi_pending;
729
    uint8_t has_error_code;
730
    uint32_t sipi_vector;
731
    uint32_t cpuid_kvm_features;
732
    uint32_t cpuid_svm_features;
733
    
734
    /* in order to simplify APIC support, we leave this pointer to the
735
       user */
736
    struct DeviceState *apic_state;
737

    
738
    uint64 mcg_cap;
739
    uint64 mcg_status;
740
    uint64 mcg_ctl;
741
    uint64 mce_banks[MCE_BANKS_DEF*4];
742

    
743
    uint64_t tsc_aux;
744

    
745
    /* vmstate */
746
    uint16_t fpus_vmstate;
747
    uint16_t fptag_vmstate;
748
    uint16_t fpregs_format_vmstate;
749

    
750
    uint64_t xstate_bv;
751
    XMMReg ymmh_regs[CPU_NB_REGS];
752

    
753
    uint64_t xcr0;
754
} CPUX86State;
755

    
756
CPUX86State *cpu_x86_init(const char *cpu_model);
757
int cpu_x86_exec(CPUX86State *s);
758
void cpu_x86_close(CPUX86State *s);
759
void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
760
                   const char *optarg);
761
void x86_cpudef_setup(void);
762

    
763
int cpu_get_pic_interrupt(CPUX86State *s);
764
/* MSDOS compatibility mode FPU exception support */
765
void cpu_set_ferr(CPUX86State *s);
766

    
767
/* this function must always be used to load data in the segment
768
   cache: it synchronizes the hflags with the segment cache values */
769
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
770
                                          int seg_reg, unsigned int selector,
771
                                          target_ulong base,
772
                                          unsigned int limit,
773
                                          unsigned int flags)
774
{
775
    SegmentCache *sc;
776
    unsigned int new_hflags;
777

    
778
    sc = &env->segs[seg_reg];
779
    sc->selector = selector;
780
    sc->base = base;
781
    sc->limit = limit;
782
    sc->flags = flags;
783

    
784
    /* update the hidden flags */
785
    {
786
        if (seg_reg == R_CS) {
787
#ifdef TARGET_X86_64
788
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
789
                /* long mode */
790
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
791
                env->hflags &= ~(HF_ADDSEG_MASK);
792
            } else
793
#endif
794
            {
795
                /* legacy / compatibility case */
796
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
797
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
798
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
799
                    new_hflags;
800
            }
801
        }
802
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
803
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
804
        if (env->hflags & HF_CS64_MASK) {
805
            /* zero base assumed for DS, ES and SS in long mode */
806
        } else if (!(env->cr[0] & CR0_PE_MASK) ||
807
                   (env->eflags & VM_MASK) ||
808
                   !(env->hflags & HF_CS32_MASK)) {
809
            /* XXX: try to avoid this test. The problem comes from the
810
               fact that is real mode or vm86 mode we only modify the
811
               'base' and 'selector' fields of the segment cache to go
812
               faster. A solution may be to force addseg to one in
813
               translate-i386.c. */
814
            new_hflags |= HF_ADDSEG_MASK;
815
        } else {
816
            new_hflags |= ((env->segs[R_DS].base |
817
                            env->segs[R_ES].base |
818
                            env->segs[R_SS].base) != 0) <<
819
                HF_ADDSEG_SHIFT;
820
        }
821
        env->hflags = (env->hflags &
822
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
823
    }
824
}
825

    
826
static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
827
                                               int sipi_vector)
828
{
829
    env->eip = 0;
830
    cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
831
                           sipi_vector << 12,
832
                           env->segs[R_CS].limit,
833
                           env->segs[R_CS].flags);
834
    env->halted = 0;
835
}
836

    
837
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
838
                            target_ulong *base, unsigned int *limit,
839
                            unsigned int *flags);
840

    
841
/* wrapper, just in case memory mappings must be changed */
842
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
843
{
844
#if HF_CPL_MASK == 3
845
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
846
#else
847
#error HF_CPL_MASK is hardcoded
848
#endif
849
}
850

    
851
/* op_helper.c */
852
/* used for debug or cpu save/restore */
853
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
854
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
855

    
856
/* cpu-exec.c */
857
/* the following helpers are only usable in user mode simulation as
858
   they can trigger unexpected exceptions */
859
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
860
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
861
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
862

    
863
/* you can call this signal handler from your SIGBUS and SIGSEGV
864
   signal handlers to inform the virtual CPU of exceptions. non zero
865
   is returned if the signal was handled by the virtual CPU.  */
866
int cpu_x86_signal_handler(int host_signum, void *pinfo,
867
                           void *puc);
868

    
869
/* cpuid.c */
870
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
871
                   uint32_t *eax, uint32_t *ebx,
872
                   uint32_t *ecx, uint32_t *edx);
873
int cpu_x86_register (CPUX86State *env, const char *cpu_model);
874
void cpu_clear_apic_feature(CPUX86State *env);
875

    
876
/* helper.c */
877
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
878
                             int is_write, int mmu_idx, int is_softmmu);
879
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
880
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
881

    
882
static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
883
{
884
    return (dr7 >> (index * 2)) & 3;
885
}
886

    
887
static inline int hw_breakpoint_type(unsigned long dr7, int index)
888
{
889
    return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
890
}
891

    
892
static inline int hw_breakpoint_len(unsigned long dr7, int index)
893
{
894
    int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
895
    return (len == 2) ? 8 : len + 1;
896
}
897

    
898
void hw_breakpoint_insert(CPUX86State *env, int index);
899
void hw_breakpoint_remove(CPUX86State *env, int index);
900
int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
901

    
902
/* will be suppressed */
903
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
904
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
905
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
906

    
907
/* hw/pc.c */
908
void cpu_smm_update(CPUX86State *env);
909
uint64_t cpu_get_tsc(CPUX86State *env);
910

    
911
/* used to debug */
912
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
913
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
914

    
915
#define TARGET_PAGE_BITS 12
916

    
917
#ifdef TARGET_X86_64
918
#define TARGET_PHYS_ADDR_SPACE_BITS 52
919
/* ??? This is really 48 bits, sign-extended, but the only thing
920
   accessible to userland with bit 48 set is the VSYSCALL, and that
921
   is handled via other mechanisms.  */
922
#define TARGET_VIRT_ADDR_SPACE_BITS 47
923
#else
924
#define TARGET_PHYS_ADDR_SPACE_BITS 36
925
#define TARGET_VIRT_ADDR_SPACE_BITS 32
926
#endif
927

    
928
#define cpu_init cpu_x86_init
929
#define cpu_exec cpu_x86_exec
930
#define cpu_gen_code cpu_x86_gen_code
931
#define cpu_signal_handler cpu_x86_signal_handler
932
#define cpu_list_id x86_cpu_list
933
#define cpudef_setup        x86_cpudef_setup
934

    
935
#define CPU_SAVE_VERSION 12
936

    
937
/* MMU modes definitions */
938
#define MMU_MODE0_SUFFIX _kernel
939
#define MMU_MODE1_SUFFIX _user
940
#define MMU_USER_IDX 1
941
static inline int cpu_mmu_index (CPUState *env)
942
{
943
    return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
944
}
945

    
946
/* translate.c */
947
void optimize_flags_init(void);
948

    
949
typedef struct CCTable {
950
    int (*compute_all)(void); /* return all the flags */
951
    int (*compute_c)(void);  /* return the C flag */
952
} CCTable;
953

    
954
#if defined(CONFIG_USER_ONLY)
955
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
956
{
957
    if (newsp)
958
        env->regs[R_ESP] = newsp;
959
    env->regs[R_EAX] = 0;
960
}
961
#endif
962

    
963
#include "cpu-all.h"
964
#include "svm.h"
965

    
966
#if !defined(CONFIG_USER_ONLY)
967
#include "hw/apic.h"
968
#endif
969

    
970
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
971
                                        target_ulong *cs_base, int *flags)
972
{
973
    *cs_base = env->segs[R_CS].base;
974
    *pc = *cs_base + env->eip;
975
    *flags = env->hflags |
976
        (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
977
}
978

    
979
void do_cpu_init(CPUState *env);
980
void do_cpu_sipi(CPUState *env);
981
#endif /* CPU_I386_H */