root / hw / sun4m.c @ c0e564d5
History | View | Annotate | Download (9.5 kB)
1 |
/*
|
---|---|
2 |
* QEMU Sun4m System Emulator
|
3 |
*
|
4 |
* Copyright (c) 2003-2005 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "vl.h" |
25 |
#include "m48t08.h" |
26 |
|
27 |
#define KERNEL_LOAD_ADDR 0x00004000 |
28 |
#define CMDLINE_ADDR 0x007ff000 |
29 |
#define INITRD_LOAD_ADDR 0x00800000 |
30 |
#define PROM_ADDR 0xffd00000 |
31 |
#define PROM_FILENAMEB "proll.bin" |
32 |
#define PROM_FILENAMEE "proll.elf" |
33 |
#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
34 |
#define PHYS_JJ_IDPROM_OFF 0x1FD8 |
35 |
#define PHYS_JJ_EEPROM_SIZE 0x2000 |
36 |
// IRQs are not PIL ones, but master interrupt controller register
|
37 |
// bits
|
38 |
#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
39 |
#define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
40 |
#define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
41 |
#define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
42 |
#define PHYS_JJ_ESP_IRQ 18 |
43 |
#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
44 |
#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
45 |
#define PHYS_JJ_LE_IRQ 16 |
46 |
#define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
47 |
#define PHYS_JJ_CLOCK_IRQ 7 |
48 |
#define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
49 |
#define PHYS_JJ_CLOCK1_IRQ 19 |
50 |
#define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
51 |
#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
52 |
#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
53 |
#define PHYS_JJ_MS_KBD_IRQ 14 |
54 |
#define PHYS_JJ_SER 0x71100000 /* Serial */ |
55 |
#define PHYS_JJ_SER_IRQ 15 |
56 |
#define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
57 |
#define PHYS_JJ_FLOPPY_IRQ 22 |
58 |
|
59 |
/* TSC handling */
|
60 |
|
61 |
uint64_t cpu_get_tsc() |
62 |
{ |
63 |
return qemu_get_clock(vm_clock);
|
64 |
} |
65 |
|
66 |
int DMA_get_channel_mode (int nchan) |
67 |
{ |
68 |
return 0; |
69 |
} |
70 |
int DMA_read_memory (int nchan, void *buf, int pos, int size) |
71 |
{ |
72 |
return 0; |
73 |
} |
74 |
int DMA_write_memory (int nchan, void *buf, int pos, int size) |
75 |
{ |
76 |
return 0; |
77 |
} |
78 |
void DMA_hold_DREQ (int nchan) {} |
79 |
void DMA_release_DREQ (int nchan) {} |
80 |
void DMA_schedule(int nchan) {} |
81 |
void DMA_run (void) {} |
82 |
void DMA_init (int high_page_enable) {} |
83 |
void DMA_register_channel (int nchan, |
84 |
DMA_transfer_handler transfer_handler, |
85 |
void *opaque)
|
86 |
{ |
87 |
} |
88 |
|
89 |
static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) |
90 |
{ |
91 |
m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
92 |
m48t08_write(nvram, addr++, value & 0xff);
|
93 |
} |
94 |
|
95 |
static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) |
96 |
{ |
97 |
m48t08_write(nvram, addr++, value >> 24);
|
98 |
m48t08_write(nvram, addr++, (value >> 16) & 0xff); |
99 |
m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
100 |
m48t08_write(nvram, addr++, value & 0xff);
|
101 |
} |
102 |
|
103 |
static void nvram_set_string (m48t08_t *nvram, uint32_t addr, |
104 |
const unsigned char *str, uint32_t max) |
105 |
{ |
106 |
unsigned int i; |
107 |
|
108 |
for (i = 0; i < max && str[i] != '\0'; i++) { |
109 |
m48t08_write(nvram, addr + i, str[i]); |
110 |
} |
111 |
m48t08_write(nvram, addr + max - 1, '\0'); |
112 |
} |
113 |
|
114 |
static m48t08_t *nvram;
|
115 |
|
116 |
extern int nographic; |
117 |
|
118 |
static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, |
119 |
int boot_device, uint32_t RAM_size,
|
120 |
uint32_t kernel_size, |
121 |
int width, int height, int depth) |
122 |
{ |
123 |
unsigned char tmp = 0; |
124 |
int i, j;
|
125 |
|
126 |
// Try to match PPC NVRAM
|
127 |
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
128 |
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
129 |
// NVRAM_size, arch not applicable
|
130 |
m48t08_write(nvram, 0x2F, nographic & 0xff); |
131 |
nvram_set_lword(nvram, 0x30, RAM_size);
|
132 |
m48t08_write(nvram, 0x34, boot_device & 0xff); |
133 |
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
|
134 |
nvram_set_lword(nvram, 0x3C, kernel_size);
|
135 |
if (cmdline) {
|
136 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
137 |
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
138 |
nvram_set_lword(nvram, 0x44, strlen(cmdline));
|
139 |
} |
140 |
// initrd_image, initrd_size passed differently
|
141 |
nvram_set_word(nvram, 0x54, width);
|
142 |
nvram_set_word(nvram, 0x56, height);
|
143 |
nvram_set_word(nvram, 0x58, depth);
|
144 |
|
145 |
// Sun4m specific use
|
146 |
i = 0x1fd8;
|
147 |
m48t08_write(nvram, i++, 0x01);
|
148 |
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
149 |
j = 0;
|
150 |
m48t08_write(nvram, i++, macaddr[j++]); |
151 |
m48t08_write(nvram, i++, macaddr[j++]); |
152 |
m48t08_write(nvram, i++, macaddr[j++]); |
153 |
m48t08_write(nvram, i++, macaddr[j++]); |
154 |
m48t08_write(nvram, i++, macaddr[j++]); |
155 |
m48t08_write(nvram, i, macaddr[j]); |
156 |
|
157 |
/* Calculate checksum */
|
158 |
for (i = 0x1fd8; i < 0x1fe7; i++) { |
159 |
tmp ^= m48t08_read(nvram, i); |
160 |
} |
161 |
m48t08_write(nvram, 0x1fe7, tmp);
|
162 |
} |
163 |
|
164 |
static void *slavio_intctl; |
165 |
|
166 |
void pic_info()
|
167 |
{ |
168 |
slavio_pic_info(slavio_intctl); |
169 |
} |
170 |
|
171 |
void irq_info()
|
172 |
{ |
173 |
slavio_irq_info(slavio_intctl); |
174 |
} |
175 |
|
176 |
void pic_set_irq(int irq, int level) |
177 |
{ |
178 |
slavio_pic_set_irq(slavio_intctl, irq, level); |
179 |
} |
180 |
|
181 |
static void *tcx; |
182 |
|
183 |
void vga_update_display()
|
184 |
{ |
185 |
tcx_update_display(tcx); |
186 |
} |
187 |
|
188 |
void vga_invalidate_display()
|
189 |
{ |
190 |
tcx_invalidate_display(tcx); |
191 |
} |
192 |
|
193 |
void vga_screen_dump(const char *filename) |
194 |
{ |
195 |
tcx_screen_dump(tcx, filename); |
196 |
} |
197 |
|
198 |
static void *iommu; |
199 |
|
200 |
uint32_t iommu_translate(uint32_t addr) |
201 |
{ |
202 |
return iommu_translate_local(iommu, addr);
|
203 |
} |
204 |
|
205 |
/* Sun4m hardware initialisation */
|
206 |
static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
207 |
DisplayState *ds, const char **fd_filename, int snapshot, |
208 |
const char *kernel_filename, const char *kernel_cmdline, |
209 |
const char *initrd_filename) |
210 |
{ |
211 |
char buf[1024]; |
212 |
int ret, linux_boot;
|
213 |
unsigned int i; |
214 |
long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
215 |
|
216 |
linux_boot = (kernel_filename != NULL);
|
217 |
|
218 |
/* allocate RAM */
|
219 |
cpu_register_physical_memory(0, ram_size, 0); |
220 |
|
221 |
iommu = iommu_init(PHYS_JJ_IOMMU); |
222 |
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
223 |
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
224 |
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
|
225 |
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
226 |
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
227 |
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
228 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
229 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
230 |
slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); |
231 |
fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
232 |
esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
233 |
|
234 |
prom_offset = ram_size + vram_size; |
235 |
|
236 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); |
237 |
ret = load_elf(buf, phys_ram_base + prom_offset); |
238 |
if (ret < 0) { |
239 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); |
240 |
ret = load_image(buf, phys_ram_base + prom_offset); |
241 |
} |
242 |
if (ret < 0) { |
243 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
244 |
buf); |
245 |
exit(1);
|
246 |
} |
247 |
cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
248 |
prom_offset | IO_MEM_ROM); |
249 |
|
250 |
kernel_size = 0;
|
251 |
if (linux_boot) {
|
252 |
kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
253 |
if (kernel_size < 0) |
254 |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
255 |
if (kernel_size < 0) |
256 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
257 |
if (kernel_size < 0) { |
258 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
259 |
kernel_filename); |
260 |
exit(1);
|
261 |
} |
262 |
|
263 |
/* load initrd */
|
264 |
initrd_size = 0;
|
265 |
if (initrd_filename) {
|
266 |
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
267 |
if (initrd_size < 0) { |
268 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
269 |
initrd_filename); |
270 |
exit(1);
|
271 |
} |
272 |
} |
273 |
if (initrd_size > 0) { |
274 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
275 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
276 |
== 0x48647253) { // HdrS |
277 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
278 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
279 |
break;
|
280 |
} |
281 |
} |
282 |
} |
283 |
} |
284 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
|
285 |
} |
286 |
|
287 |
QEMUMachine sun4m_machine = { |
288 |
"sun4m",
|
289 |
"Sun4m platform",
|
290 |
sun4m_init, |
291 |
}; |