Revision c1713132 target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 492 | 492 |
gen_op_vfp_setreg_F0s(vfp_reg_offset(dp, reg)); |
| 493 | 493 |
} |
| 494 | 494 |
|
| 495 |
/* Disassemble system coprocessor instruction. Return nonzero if |
|
| 496 |
instruction is not defined. */ |
|
| 497 |
static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) |
|
| 498 |
{
|
|
| 499 |
uint32_t rd = (insn >> 12) & 0xf; |
|
| 500 |
uint32_t cp = (insn >> 8) & 0xf; |
|
| 501 |
if (IS_USER(s)) {
|
|
| 502 |
return 1; |
|
| 503 |
} |
|
| 504 |
|
|
| 505 |
if (insn & (1 << 20)) {
|
|
| 506 |
if (!env->cp[cp].cp_read) |
|
| 507 |
return 1; |
|
| 508 |
gen_op_movl_T0_im((uint32_t) s->pc); |
|
| 509 |
gen_op_movl_reg_TN[0][15](); |
|
| 510 |
gen_op_movl_T0_cp(insn); |
|
| 511 |
gen_movl_reg_T0(s, rd); |
|
| 512 |
} else {
|
|
| 513 |
if (!env->cp[cp].cp_write) |
|
| 514 |
return 1; |
|
| 515 |
gen_op_movl_T0_im((uint32_t) s->pc); |
|
| 516 |
gen_op_movl_reg_TN[0][15](); |
|
| 517 |
gen_movl_T0_reg(s, rd); |
|
| 518 |
gen_op_movl_cp_T0(insn); |
|
| 519 |
} |
|
| 520 |
return 0; |
|
| 521 |
} |
|
| 522 |
|
|
| 495 | 523 |
/* Disassemble system coprocessor (cp15) instruction. Return nonzero if |
| 496 | 524 |
instruction is not defined. */ |
| 497 | 525 |
static int disas_cp15_insn(DisasContext *s, uint32_t insn) |
| ... | ... | |
| 1812 | 1840 |
case 0xe: |
| 1813 | 1841 |
/* Coprocessor. */ |
| 1814 | 1842 |
op1 = (insn >> 8) & 0xf; |
| 1843 |
if (arm_feature(env, ARM_FEATURE_XSCALE) && |
|
| 1844 |
((env->cp15.c15_cpar ^ 0x3fff) & (1 << op1))) |
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| 1845 |
goto illegal_op; |
|
| 1815 | 1846 |
switch (op1) {
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| 1847 |
case 0 ... 1: |
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| 1848 |
case 2 ... 9: |
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| 1849 |
case 12 ... 14: |
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| 1850 |
if (disas_cp_insn (env, s, insn)) |
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| 1851 |
goto illegal_op; |
|
| 1852 |
break; |
|
| 1816 | 1853 |
case 10: |
| 1817 | 1854 |
case 11: |
| 1818 | 1855 |
if (disas_vfp_insn (env, s, insn)) |
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