root / target-arm / helper.c @ c1713132
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#include <stdio.h> |
---|---|
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "exec-all.h" |
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|
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static inline void set_feature(CPUARMState *env, int feature) |
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{ |
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env->features |= 1u << feature;
|
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} |
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|
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static void cpu_reset_model_id(CPUARMState *env, uint32_t id) |
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{ |
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env->cp15.c0_cpuid = id; |
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switch (id) {
|
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case ARM_CPUID_ARM926:
|
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set_feature(env, ARM_FEATURE_VFP); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
|
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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break;
|
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case ARM_CPUID_ARM1026:
|
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
|
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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break;
|
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case ARM_CPUID_PXA250:
|
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case ARM_CPUID_PXA255:
|
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case ARM_CPUID_PXA260:
|
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case ARM_CPUID_PXA261:
|
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case ARM_CPUID_PXA262:
|
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set_feature(env, ARM_FEATURE_XSCALE); |
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/* JTAG_ID is ((id << 28) | 0x09265013) */
|
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env->cp15.c0_cachetype = 0xd172172;
|
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break;
|
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case ARM_CPUID_PXA270_A0:
|
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case ARM_CPUID_PXA270_A1:
|
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case ARM_CPUID_PXA270_B0:
|
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case ARM_CPUID_PXA270_B1:
|
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case ARM_CPUID_PXA270_C0:
|
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case ARM_CPUID_PXA270_C5:
|
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set_feature(env, ARM_FEATURE_XSCALE); |
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/* JTAG_ID is ((id << 28) | 0x09265013) */
|
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env->cp15.c0_cachetype = 0xd172172;
|
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break;
|
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default:
|
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cpu_abort(env, "Bad CPU ID: %x\n", id);
|
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break;
|
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} |
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} |
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|
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void cpu_reset(CPUARMState *env)
|
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{ |
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uint32_t id; |
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id = env->cp15.c0_cpuid; |
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memset(env, 0, offsetof(CPUARMState, breakpoints));
|
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if (id)
|
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cpu_reset_model_id(env, id); |
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#if defined (CONFIG_USER_ONLY)
|
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
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#else
|
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/* SVC mode with interrupts disabled. */
|
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
|
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#endif
|
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env->regs[15] = 0; |
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tlb_flush(env, 1);
|
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} |
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|
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CPUARMState *cpu_arm_init(void)
|
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{ |
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CPUARMState *env; |
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|
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env = qemu_mallocz(sizeof(CPUARMState));
|
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if (!env)
|
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return NULL; |
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cpu_exec_init(env); |
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cpu_reset(env); |
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return env;
|
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} |
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|
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struct arm_cpu_t {
|
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uint32_t id; |
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const char *name; |
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}; |
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|
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static const struct arm_cpu_t arm_cpu_names[] = { |
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{ ARM_CPUID_ARM926, "arm926"},
|
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{ ARM_CPUID_ARM1026, "arm1026"},
|
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{ ARM_CPUID_PXA250, "pxa250" },
|
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{ ARM_CPUID_PXA255, "pxa255" },
|
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{ ARM_CPUID_PXA260, "pxa260" },
|
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{ ARM_CPUID_PXA261, "pxa261" },
|
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{ ARM_CPUID_PXA262, "pxa262" },
|
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{ ARM_CPUID_PXA270, "pxa270" },
|
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{ ARM_CPUID_PXA270_A0, "pxa270-a0" },
|
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{ ARM_CPUID_PXA270_A1, "pxa270-a1" },
|
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{ ARM_CPUID_PXA270_B0, "pxa270-b0" },
|
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{ ARM_CPUID_PXA270_B1, "pxa270-b1" },
|
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{ ARM_CPUID_PXA270_C0, "pxa270-c0" },
|
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{ ARM_CPUID_PXA270_C5, "pxa270-c5" },
|
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{ 0, NULL} |
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}; |
106 |
|
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void arm_cpu_list(void) |
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{ |
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int i;
|
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|
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printf ("Available CPUs:\n");
|
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for (i = 0; arm_cpu_names[i].name; i++) { |
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printf(" %s\n", arm_cpu_names[i].name);
|
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} |
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} |
116 |
|
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void cpu_arm_set_model(CPUARMState *env, const char *name) |
118 |
{ |
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int i;
|
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uint32_t id; |
121 |
|
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id = 0;
|
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i = 0;
|
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for (i = 0; arm_cpu_names[i].name; i++) { |
125 |
if (strcmp(name, arm_cpu_names[i].name) == 0) { |
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id = arm_cpu_names[i].id; |
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break;
|
128 |
} |
129 |
} |
130 |
if (!id) {
|
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cpu_abort(env, "Unknown CPU '%s'", name);
|
132 |
return;
|
133 |
} |
134 |
cpu_reset_model_id(env, id); |
135 |
} |
136 |
|
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void cpu_arm_close(CPUARMState *env)
|
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{ |
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free(env); |
140 |
} |
141 |
|
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#if defined(CONFIG_USER_ONLY)
|
143 |
|
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void do_interrupt (CPUState *env)
|
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{ |
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env->exception_index = -1;
|
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} |
148 |
|
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
150 |
int is_user, int is_softmmu) |
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{ |
152 |
if (rw == 2) { |
153 |
env->exception_index = EXCP_PREFETCH_ABORT; |
154 |
env->cp15.c6_insn = address; |
155 |
} else {
|
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env->exception_index = EXCP_DATA_ABORT; |
157 |
env->cp15.c6_data = address; |
158 |
} |
159 |
return 1; |
160 |
} |
161 |
|
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
163 |
{ |
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return addr;
|
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} |
166 |
|
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/* These should probably raise undefined insn exceptions. */
|
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void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
|
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{ |
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int op1 = (insn >> 8) & 0xf; |
171 |
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
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return;
|
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} |
174 |
|
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uint32_t helper_get_cp(CPUState *env, uint32_t insn) |
176 |
{ |
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int op1 = (insn >> 8) & 0xf; |
178 |
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
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return 0; |
180 |
} |
181 |
|
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void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
|
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{ |
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cpu_abort(env, "cp15 insn %08x\n", insn);
|
185 |
} |
186 |
|
187 |
uint32_t helper_get_cp15(CPUState *env, uint32_t insn) |
188 |
{ |
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cpu_abort(env, "cp15 insn %08x\n", insn);
|
190 |
return 0; |
191 |
} |
192 |
|
193 |
void switch_mode(CPUState *env, int mode) |
194 |
{ |
195 |
if (mode != ARM_CPU_MODE_USR)
|
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cpu_abort(env, "Tried to switch out of user mode\n");
|
197 |
} |
198 |
|
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#else
|
200 |
|
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extern int semihosting_enabled; |
202 |
|
203 |
/* Map CPU modes onto saved register banks. */
|
204 |
static inline int bank_number (int mode) |
205 |
{ |
206 |
switch (mode) {
|
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case ARM_CPU_MODE_USR:
|
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case ARM_CPU_MODE_SYS:
|
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return 0; |
210 |
case ARM_CPU_MODE_SVC:
|
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return 1; |
212 |
case ARM_CPU_MODE_ABT:
|
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return 2; |
214 |
case ARM_CPU_MODE_UND:
|
215 |
return 3; |
216 |
case ARM_CPU_MODE_IRQ:
|
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return 4; |
218 |
case ARM_CPU_MODE_FIQ:
|
219 |
return 5; |
220 |
} |
221 |
cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
|
222 |
return -1; |
223 |
} |
224 |
|
225 |
void switch_mode(CPUState *env, int mode) |
226 |
{ |
227 |
int old_mode;
|
228 |
int i;
|
229 |
|
230 |
old_mode = env->uncached_cpsr & CPSR_M; |
231 |
if (mode == old_mode)
|
232 |
return;
|
233 |
|
234 |
if (old_mode == ARM_CPU_MODE_FIQ) {
|
235 |
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
236 |
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
237 |
} else if (mode == ARM_CPU_MODE_FIQ) { |
238 |
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
239 |
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
240 |
} |
241 |
|
242 |
i = bank_number(old_mode); |
243 |
env->banked_r13[i] = env->regs[13];
|
244 |
env->banked_r14[i] = env->regs[14];
|
245 |
env->banked_spsr[i] = env->spsr; |
246 |
|
247 |
i = bank_number(mode); |
248 |
env->regs[13] = env->banked_r13[i];
|
249 |
env->regs[14] = env->banked_r14[i];
|
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env->spsr = env->banked_spsr[i]; |
251 |
} |
252 |
|
253 |
/* Handle a CPU exception. */
|
254 |
void do_interrupt(CPUARMState *env)
|
255 |
{ |
256 |
uint32_t addr; |
257 |
uint32_t mask; |
258 |
int new_mode;
|
259 |
uint32_t offset; |
260 |
|
261 |
/* TODO: Vectored interrupt controller. */
|
262 |
switch (env->exception_index) {
|
263 |
case EXCP_UDEF:
|
264 |
new_mode = ARM_CPU_MODE_UND; |
265 |
addr = 0x04;
|
266 |
mask = CPSR_I; |
267 |
if (env->thumb)
|
268 |
offset = 2;
|
269 |
else
|
270 |
offset = 4;
|
271 |
break;
|
272 |
case EXCP_SWI:
|
273 |
if (semihosting_enabled) {
|
274 |
/* Check for semihosting interrupt. */
|
275 |
if (env->thumb) {
|
276 |
mask = lduw_code(env->regs[15] - 2) & 0xff; |
277 |
} else {
|
278 |
mask = ldl_code(env->regs[15] - 4) & 0xffffff; |
279 |
} |
280 |
/* Only intercept calls from privileged modes, to provide some
|
281 |
semblance of security. */
|
282 |
if (((mask == 0x123456 && !env->thumb) |
283 |
|| (mask == 0xab && env->thumb))
|
284 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
285 |
env->regs[0] = do_arm_semihosting(env);
|
286 |
return;
|
287 |
} |
288 |
} |
289 |
new_mode = ARM_CPU_MODE_SVC; |
290 |
addr = 0x08;
|
291 |
mask = CPSR_I; |
292 |
/* The PC already points to the next instructon. */
|
293 |
offset = 0;
|
294 |
break;
|
295 |
case EXCP_PREFETCH_ABORT:
|
296 |
case EXCP_BKPT:
|
297 |
new_mode = ARM_CPU_MODE_ABT; |
298 |
addr = 0x0c;
|
299 |
mask = CPSR_A | CPSR_I; |
300 |
offset = 4;
|
301 |
break;
|
302 |
case EXCP_DATA_ABORT:
|
303 |
new_mode = ARM_CPU_MODE_ABT; |
304 |
addr = 0x10;
|
305 |
mask = CPSR_A | CPSR_I; |
306 |
offset = 8;
|
307 |
break;
|
308 |
case EXCP_IRQ:
|
309 |
new_mode = ARM_CPU_MODE_IRQ; |
310 |
addr = 0x18;
|
311 |
/* Disable IRQ and imprecise data aborts. */
|
312 |
mask = CPSR_A | CPSR_I; |
313 |
offset = 4;
|
314 |
break;
|
315 |
case EXCP_FIQ:
|
316 |
new_mode = ARM_CPU_MODE_FIQ; |
317 |
addr = 0x1c;
|
318 |
/* Disable FIQ, IRQ and imprecise data aborts. */
|
319 |
mask = CPSR_A | CPSR_I | CPSR_F; |
320 |
offset = 4;
|
321 |
break;
|
322 |
default:
|
323 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
324 |
return; /* Never happens. Keep compiler happy. */ |
325 |
} |
326 |
/* High vectors. */
|
327 |
if (env->cp15.c1_sys & (1 << 13)) { |
328 |
addr += 0xffff0000;
|
329 |
} |
330 |
switch_mode (env, new_mode); |
331 |
env->spsr = cpsr_read(env); |
332 |
/* Switch to the new mode, and switch to Arm mode. */
|
333 |
/* ??? Thumb interrupt handlers not implemented. */
|
334 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
335 |
env->uncached_cpsr |= mask; |
336 |
env->thumb = 0;
|
337 |
env->regs[14] = env->regs[15] + offset; |
338 |
env->regs[15] = addr;
|
339 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
340 |
} |
341 |
|
342 |
/* Check section/page access permissions.
|
343 |
Returns the page protection flags, or zero if the access is not
|
344 |
permitted. */
|
345 |
static inline int check_ap(CPUState *env, int ap, int domain, int access_type, |
346 |
int is_user)
|
347 |
{ |
348 |
if (domain == 3) |
349 |
return PAGE_READ | PAGE_WRITE;
|
350 |
|
351 |
switch (ap) {
|
352 |
case 0: |
353 |
if (access_type == 1) |
354 |
return 0; |
355 |
switch ((env->cp15.c1_sys >> 8) & 3) { |
356 |
case 1: |
357 |
return is_user ? 0 : PAGE_READ; |
358 |
case 2: |
359 |
return PAGE_READ;
|
360 |
default:
|
361 |
return 0; |
362 |
} |
363 |
case 1: |
364 |
return is_user ? 0 : PAGE_READ | PAGE_WRITE; |
365 |
case 2: |
366 |
if (is_user)
|
367 |
return (access_type == 1) ? 0 : PAGE_READ; |
368 |
else
|
369 |
return PAGE_READ | PAGE_WRITE;
|
370 |
case 3: |
371 |
return PAGE_READ | PAGE_WRITE;
|
372 |
default:
|
373 |
abort(); |
374 |
} |
375 |
} |
376 |
|
377 |
static int get_phys_addr(CPUState *env, uint32_t address, int access_type, |
378 |
int is_user, uint32_t *phys_ptr, int *prot) |
379 |
{ |
380 |
int code;
|
381 |
uint32_t table; |
382 |
uint32_t desc; |
383 |
int type;
|
384 |
int ap;
|
385 |
int domain;
|
386 |
uint32_t phys_addr; |
387 |
|
388 |
/* Fast Context Switch Extension. */
|
389 |
if (address < 0x02000000) |
390 |
address += env->cp15.c13_fcse; |
391 |
|
392 |
if ((env->cp15.c1_sys & 1) == 0) { |
393 |
/* MMU diusabled. */
|
394 |
*phys_ptr = address; |
395 |
*prot = PAGE_READ | PAGE_WRITE; |
396 |
} else {
|
397 |
/* Pagetable walk. */
|
398 |
/* Lookup l1 descriptor. */
|
399 |
table = (env->cp15.c2 & 0xffffc000) | ((address >> 18) & 0x3ffc); |
400 |
desc = ldl_phys(table); |
401 |
type = (desc & 3);
|
402 |
domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; |
403 |
if (type == 0) { |
404 |
/* Secton translation fault. */
|
405 |
code = 5;
|
406 |
goto do_fault;
|
407 |
} |
408 |
if (domain == 0 || domain == 2) { |
409 |
if (type == 2) |
410 |
code = 9; /* Section domain fault. */ |
411 |
else
|
412 |
code = 11; /* Page domain fault. */ |
413 |
goto do_fault;
|
414 |
} |
415 |
if (type == 2) { |
416 |
/* 1Mb section. */
|
417 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
418 |
ap = (desc >> 10) & 3; |
419 |
code = 13;
|
420 |
} else {
|
421 |
/* Lookup l2 entry. */
|
422 |
if (type == 1) { |
423 |
/* Coarse pagetable. */
|
424 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
425 |
} else {
|
426 |
/* Fine pagetable. */
|
427 |
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); |
428 |
} |
429 |
desc = ldl_phys(table); |
430 |
switch (desc & 3) { |
431 |
case 0: /* Page translation fault. */ |
432 |
code = 7;
|
433 |
goto do_fault;
|
434 |
case 1: /* 64k page. */ |
435 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
436 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
437 |
break;
|
438 |
case 2: /* 4k page. */ |
439 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
440 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
441 |
break;
|
442 |
case 3: /* 1k page. */ |
443 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
444 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
445 |
else {
|
446 |
if (type == 1) { |
447 |
/* Page translation fault. */
|
448 |
code = 7;
|
449 |
goto do_fault;
|
450 |
} |
451 |
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); |
452 |
} |
453 |
ap = (desc >> 4) & 3; |
454 |
break;
|
455 |
default:
|
456 |
/* Never happens, but compiler isn't smart enough to tell. */
|
457 |
abort(); |
458 |
} |
459 |
code = 15;
|
460 |
} |
461 |
*prot = check_ap(env, ap, domain, access_type, is_user); |
462 |
if (!*prot) {
|
463 |
/* Access permission fault. */
|
464 |
goto do_fault;
|
465 |
} |
466 |
*phys_ptr = phys_addr; |
467 |
} |
468 |
return 0; |
469 |
do_fault:
|
470 |
return code | (domain << 4); |
471 |
} |
472 |
|
473 |
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
|
474 |
int access_type, int is_user, int is_softmmu) |
475 |
{ |
476 |
uint32_t phys_addr; |
477 |
int prot;
|
478 |
int ret;
|
479 |
|
480 |
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot); |
481 |
if (ret == 0) { |
482 |
/* Map a single [sub]page. */
|
483 |
phys_addr &= ~(uint32_t)0x3ff;
|
484 |
address &= ~(uint32_t)0x3ff;
|
485 |
return tlb_set_page (env, address, phys_addr, prot, is_user,
|
486 |
is_softmmu); |
487 |
} |
488 |
|
489 |
if (access_type == 2) { |
490 |
env->cp15.c5_insn = ret; |
491 |
env->cp15.c6_insn = address; |
492 |
env->exception_index = EXCP_PREFETCH_ABORT; |
493 |
} else {
|
494 |
env->cp15.c5_data = ret; |
495 |
env->cp15.c6_data = address; |
496 |
env->exception_index = EXCP_DATA_ABORT; |
497 |
} |
498 |
return 1; |
499 |
} |
500 |
|
501 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
502 |
{ |
503 |
uint32_t phys_addr; |
504 |
int prot;
|
505 |
int ret;
|
506 |
|
507 |
ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot); |
508 |
|
509 |
if (ret != 0) |
510 |
return -1; |
511 |
|
512 |
return phys_addr;
|
513 |
} |
514 |
|
515 |
void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
|
516 |
{ |
517 |
int cp_num = (insn >> 8) & 0xf; |
518 |
int cp_info = (insn >> 5) & 7; |
519 |
int src = (insn >> 16) & 0xf; |
520 |
int operand = insn & 0xf; |
521 |
|
522 |
if (env->cp[cp_num].cp_write)
|
523 |
env->cp[cp_num].cp_write(env->cp[cp_num].opaque, |
524 |
cp_info, src, operand, val); |
525 |
} |
526 |
|
527 |
uint32_t helper_get_cp(CPUState *env, uint32_t insn) |
528 |
{ |
529 |
int cp_num = (insn >> 8) & 0xf; |
530 |
int cp_info = (insn >> 5) & 7; |
531 |
int dest = (insn >> 16) & 0xf; |
532 |
int operand = insn & 0xf; |
533 |
|
534 |
if (env->cp[cp_num].cp_read)
|
535 |
return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
|
536 |
cp_info, dest, operand); |
537 |
return 0; |
538 |
} |
539 |
|
540 |
void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
|
541 |
{ |
542 |
uint32_t op2; |
543 |
|
544 |
op2 = (insn >> 5) & 7; |
545 |
switch ((insn >> 16) & 0xf) { |
546 |
case 0: /* ID codes. */ |
547 |
goto bad_reg;
|
548 |
case 1: /* System configuration. */ |
549 |
switch (op2) {
|
550 |
case 0: |
551 |
if (!arm_feature(env, ARM_FEATURE_XSCALE) || (insn & 0xf) == 0) |
552 |
env->cp15.c1_sys = val; |
553 |
/* ??? Lots of these bits are not implemented. */
|
554 |
/* This may enable/disable the MMU, so do a TLB flush. */
|
555 |
tlb_flush(env, 1);
|
556 |
break;
|
557 |
case 1: |
558 |
/* XScale doesn't implement AUX CR (P-Bit) but allows
|
559 |
* writing with zero and reading. */
|
560 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
561 |
break;
|
562 |
goto bad_reg;
|
563 |
case 2: |
564 |
env->cp15.c1_coproc = val; |
565 |
/* ??? Is this safe when called from within a TB? */
|
566 |
tb_flush(env); |
567 |
break;
|
568 |
default:
|
569 |
goto bad_reg;
|
570 |
} |
571 |
break;
|
572 |
case 2: /* MMU Page table control. */ |
573 |
env->cp15.c2 = val; |
574 |
break;
|
575 |
case 3: /* MMU Domain access control. */ |
576 |
env->cp15.c3 = val; |
577 |
break;
|
578 |
case 4: /* Reserved. */ |
579 |
goto bad_reg;
|
580 |
case 5: /* MMU Fault status. */ |
581 |
switch (op2) {
|
582 |
case 0: |
583 |
env->cp15.c5_data = val; |
584 |
break;
|
585 |
case 1: |
586 |
env->cp15.c5_insn = val; |
587 |
break;
|
588 |
default:
|
589 |
goto bad_reg;
|
590 |
} |
591 |
break;
|
592 |
case 6: /* MMU Fault address. */ |
593 |
switch (op2) {
|
594 |
case 0: |
595 |
env->cp15.c6_data = val; |
596 |
break;
|
597 |
case 1: |
598 |
env->cp15.c6_insn = val; |
599 |
break;
|
600 |
default:
|
601 |
goto bad_reg;
|
602 |
} |
603 |
break;
|
604 |
case 7: /* Cache control. */ |
605 |
/* No cache, so nothing to do. */
|
606 |
break;
|
607 |
case 8: /* MMU TLB control. */ |
608 |
switch (op2) {
|
609 |
case 0: /* Invalidate all. */ |
610 |
tlb_flush(env, 0);
|
611 |
break;
|
612 |
case 1: /* Invalidate single TLB entry. */ |
613 |
#if 0
|
614 |
/* ??? This is wrong for large pages and sections. */
|
615 |
/* As an ugly hack to make linux work we always flush a 4K
|
616 |
pages. */
|
617 |
val &= 0xfffff000;
|
618 |
tlb_flush_page(env, val);
|
619 |
tlb_flush_page(env, val + 0x400);
|
620 |
tlb_flush_page(env, val + 0x800);
|
621 |
tlb_flush_page(env, val + 0xc00);
|
622 |
#else
|
623 |
tlb_flush(env, 1);
|
624 |
#endif
|
625 |
break;
|
626 |
default:
|
627 |
goto bad_reg;
|
628 |
} |
629 |
break;
|
630 |
case 9: /* Cache lockdown. */ |
631 |
switch (op2) {
|
632 |
case 0: |
633 |
env->cp15.c9_data = val; |
634 |
break;
|
635 |
case 1: |
636 |
env->cp15.c9_insn = val; |
637 |
break;
|
638 |
default:
|
639 |
goto bad_reg;
|
640 |
} |
641 |
break;
|
642 |
case 10: /* MMU TLB lockdown. */ |
643 |
/* ??? TLB lockdown not implemented. */
|
644 |
break;
|
645 |
case 11: /* TCM DMA control. */ |
646 |
case 12: /* Reserved. */ |
647 |
goto bad_reg;
|
648 |
case 13: /* Process ID. */ |
649 |
switch (op2) {
|
650 |
case 0: |
651 |
/* Unlike real hardware the qemu TLB uses virtual addresses,
|
652 |
not modified virtual addresses, so this causes a TLB flush.
|
653 |
*/
|
654 |
if (env->cp15.c13_fcse != val)
|
655 |
tlb_flush(env, 1);
|
656 |
env->cp15.c13_fcse = val; |
657 |
break;
|
658 |
case 1: |
659 |
/* This changes the ASID, so do a TLB flush. */
|
660 |
if (env->cp15.c13_context != val)
|
661 |
tlb_flush(env, 0);
|
662 |
env->cp15.c13_context = val; |
663 |
break;
|
664 |
default:
|
665 |
goto bad_reg;
|
666 |
} |
667 |
break;
|
668 |
case 14: /* Reserved. */ |
669 |
goto bad_reg;
|
670 |
case 15: /* Implementation specific. */ |
671 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
672 |
if (op2 == 0 && (insn & 0xf) == 1) { |
673 |
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
674 |
tb_flush(env); |
675 |
env->cp15.c15_cpar = (val & 0x3fff) | 2; |
676 |
break;
|
677 |
} |
678 |
goto bad_reg;
|
679 |
} |
680 |
break;
|
681 |
} |
682 |
return;
|
683 |
bad_reg:
|
684 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
685 |
cpu_abort(env, "Unimplemented cp15 register write\n");
|
686 |
} |
687 |
|
688 |
uint32_t helper_get_cp15(CPUState *env, uint32_t insn) |
689 |
{ |
690 |
uint32_t op2; |
691 |
|
692 |
op2 = (insn >> 5) & 7; |
693 |
switch ((insn >> 16) & 0xf) { |
694 |
case 0: /* ID codes. */ |
695 |
switch (op2) {
|
696 |
default: /* Device ID. */ |
697 |
return env->cp15.c0_cpuid;
|
698 |
case 1: /* Cache Type. */ |
699 |
return env->cp15.c0_cachetype;
|
700 |
case 2: /* TCM status. */ |
701 |
return 0; |
702 |
} |
703 |
case 1: /* System configuration. */ |
704 |
switch (op2) {
|
705 |
case 0: /* Control register. */ |
706 |
return env->cp15.c1_sys;
|
707 |
case 1: /* Auxiliary control register. */ |
708 |
if (arm_feature(env, ARM_FEATURE_AUXCR))
|
709 |
return 1; |
710 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
711 |
return 0; |
712 |
goto bad_reg;
|
713 |
case 2: /* Coprocessor access register. */ |
714 |
return env->cp15.c1_coproc;
|
715 |
default:
|
716 |
goto bad_reg;
|
717 |
} |
718 |
case 2: /* MMU Page table control. */ |
719 |
return env->cp15.c2;
|
720 |
case 3: /* MMU Domain access control. */ |
721 |
return env->cp15.c3;
|
722 |
case 4: /* Reserved. */ |
723 |
goto bad_reg;
|
724 |
case 5: /* MMU Fault status. */ |
725 |
switch (op2) {
|
726 |
case 0: |
727 |
return env->cp15.c5_data;
|
728 |
case 1: |
729 |
return env->cp15.c5_insn;
|
730 |
default:
|
731 |
goto bad_reg;
|
732 |
} |
733 |
case 6: /* MMU Fault address. */ |
734 |
switch (op2) {
|
735 |
case 0: |
736 |
return env->cp15.c6_data;
|
737 |
case 1: |
738 |
/* Arm9 doesn't have an IFAR, but implementing it anyway shouldn't
|
739 |
do any harm. */
|
740 |
return env->cp15.c6_insn;
|
741 |
default:
|
742 |
goto bad_reg;
|
743 |
} |
744 |
case 7: /* Cache control. */ |
745 |
/* ??? This is for test, clean and invaidate operations that set the
|
746 |
Z flag. We can't represent N = Z = 1, so it also clears
|
747 |
the N flag. Oh well. */
|
748 |
env->NZF = 0;
|
749 |
return 0; |
750 |
case 8: /* MMU TLB control. */ |
751 |
goto bad_reg;
|
752 |
case 9: /* Cache lockdown. */ |
753 |
switch (op2) {
|
754 |
case 0: |
755 |
return env->cp15.c9_data;
|
756 |
case 1: |
757 |
return env->cp15.c9_insn;
|
758 |
default:
|
759 |
goto bad_reg;
|
760 |
} |
761 |
case 10: /* MMU TLB lockdown. */ |
762 |
/* ??? TLB lockdown not implemented. */
|
763 |
return 0; |
764 |
case 11: /* TCM DMA control. */ |
765 |
case 12: /* Reserved. */ |
766 |
goto bad_reg;
|
767 |
case 13: /* Process ID. */ |
768 |
switch (op2) {
|
769 |
case 0: |
770 |
return env->cp15.c13_fcse;
|
771 |
case 1: |
772 |
return env->cp15.c13_context;
|
773 |
default:
|
774 |
goto bad_reg;
|
775 |
} |
776 |
case 14: /* Reserved. */ |
777 |
goto bad_reg;
|
778 |
case 15: /* Implementation specific. */ |
779 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
780 |
if (op2 == 0 && (insn & 0xf) == 1) |
781 |
return env->cp15.c15_cpar;
|
782 |
|
783 |
goto bad_reg;
|
784 |
} |
785 |
return 0; |
786 |
} |
787 |
bad_reg:
|
788 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
789 |
cpu_abort(env, "Unimplemented cp15 register read\n");
|
790 |
return 0; |
791 |
} |
792 |
|
793 |
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
794 |
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
795 |
void *opaque)
|
796 |
{ |
797 |
if (cpnum < 0 || cpnum > 14) { |
798 |
cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
|
799 |
return;
|
800 |
} |
801 |
|
802 |
env->cp[cpnum].cp_read = cp_read; |
803 |
env->cp[cpnum].cp_write = cp_write; |
804 |
env->cp[cpnum].opaque = opaque; |
805 |
} |
806 |
|
807 |
#endif
|