Revision c19148bd target-sparc/helper.c
| b/target-sparc/helper.c | ||
|---|---|---|
| 48 | 48 |
uint32_t mmu_trcr_mask; |
| 49 | 49 |
uint32_t features; |
| 50 | 50 |
uint32_t nwindows; |
| 51 |
uint32_t maxtl; |
|
| 51 | 52 |
}; |
| 52 | 53 |
|
| 53 | 54 |
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
| ... | ... | |
| 738 | 739 |
} |
| 739 | 740 |
#endif |
| 740 | 741 |
#if !defined(CONFIG_USER_ONLY) |
| 741 |
if (env->tl == MAXTL) {
|
|
| 742 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
|
|
| 743 |
env->exception_index);
|
|
| 742 |
if (env->tl >= env->maxtl) {
|
|
| 743 |
cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
|
|
| 744 |
" Error state", env->exception_index, env->tl, env->maxtl);
|
|
| 744 | 745 |
return; |
| 745 | 746 |
} |
| 746 | 747 |
#endif |
| 747 |
if (env->tl < MAXTL - 1) {
|
|
| 748 |
if (env->tl < env->maxtl - 1) {
|
|
| 748 | 749 |
env->tl++; |
| 749 | 750 |
} else {
|
| 750 | 751 |
env->pstate |= PS_RED; |
| 751 |
if (env->tl != MAXTL)
|
|
| 752 |
if (env->tl < env->maxtl)
|
|
| 752 | 753 |
env->tl++; |
| 753 | 754 |
} |
| 754 |
env->tsptr = &env->ts[env->tl]; |
|
| 755 |
env->tsptr = &env->ts[env->tl & MAXTL_MASK];
|
|
| 755 | 756 |
env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | |
| 756 | 757 |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
| 757 | 758 |
GET_CWP64(env); |
| ... | ... | |
| 918 | 919 |
env->pstate = PS_PRIV; |
| 919 | 920 |
env->hpstate = HS_PRIV; |
| 920 | 921 |
env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset |
| 921 |
env->tsptr = &env->ts[env->tl]; |
|
| 922 |
env->tsptr = &env->ts[env->tl & MAXTL_MASK];
|
|
| 922 | 923 |
#else |
| 923 | 924 |
env->pc = 0; |
| 924 | 925 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
| ... | ... | |
| 950 | 951 |
cpu_sparc_set_id(env, 0); |
| 951 | 952 |
#else |
| 952 | 953 |
env->mmu_version = def->mmu_version; |
| 954 |
env->maxtl = def->maxtl; |
|
| 955 |
env->version |= def->maxtl << 8; |
|
| 953 | 956 |
env->version |= def->nwindows - 1; |
| 954 | 957 |
#endif |
| 955 | 958 |
return 0; |
| ... | ... | |
| 991 | 994 |
#ifdef TARGET_SPARC64 |
| 992 | 995 |
{
|
| 993 | 996 |
.name = "Fujitsu Sparc64", |
| 994 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
|
| 995 |
| (MAXTL << 8)), |
|
| 997 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
|
| 996 | 998 |
.fpu_version = 0x00000000, |
| 997 | 999 |
.mmu_version = mmu_us_12, |
| 998 | 1000 |
.nwindows = 4, |
| 1001 |
.maxtl = 4, |
|
| 999 | 1002 |
.features = CPU_DEFAULT_FEATURES, |
| 1000 | 1003 |
}, |
| 1001 | 1004 |
{
|
| 1002 | 1005 |
.name = "Fujitsu Sparc64 III", |
| 1003 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
|
| 1004 |
| (MAXTL << 8)), |
|
| 1006 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
|
| 1005 | 1007 |
.fpu_version = 0x00000000, |
| 1006 | 1008 |
.mmu_version = mmu_us_12, |
| 1007 | 1009 |
.nwindows = 5, |
| 1010 |
.maxtl = 4, |
|
| 1008 | 1011 |
.features = CPU_DEFAULT_FEATURES, |
| 1009 | 1012 |
}, |
| 1010 | 1013 |
{
|
| 1011 | 1014 |
.name = "Fujitsu Sparc64 IV", |
| 1012 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
|
| 1013 |
| (MAXTL << 8)), |
|
| 1015 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
|
| 1014 | 1016 |
.fpu_version = 0x00000000, |
| 1015 | 1017 |
.mmu_version = mmu_us_12, |
| 1016 | 1018 |
.nwindows = 8, |
| 1019 |
.maxtl = 5, |
|
| 1017 | 1020 |
.features = CPU_DEFAULT_FEATURES, |
| 1018 | 1021 |
}, |
| 1019 | 1022 |
{
|
| 1020 | 1023 |
.name = "Fujitsu Sparc64 V", |
| 1021 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
|
| 1022 |
| (MAXTL << 8)), |
|
| 1024 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
|
| 1023 | 1025 |
.fpu_version = 0x00000000, |
| 1024 | 1026 |
.mmu_version = mmu_us_12, |
| 1025 | 1027 |
.nwindows = 8, |
| 1028 |
.maxtl = 5, |
|
| 1026 | 1029 |
.features = CPU_DEFAULT_FEATURES, |
| 1027 | 1030 |
}, |
| 1028 | 1031 |
{
|
| 1029 | 1032 |
.name = "TI UltraSparc I", |
| 1030 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
|
| 1031 |
| (MAXTL << 8)), |
|
| 1033 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
|
| 1032 | 1034 |
.fpu_version = 0x00000000, |
| 1033 | 1035 |
.mmu_version = mmu_us_12, |
| 1034 | 1036 |
.nwindows = 8, |
| 1037 |
.maxtl = 5, |
|
| 1035 | 1038 |
.features = CPU_DEFAULT_FEATURES, |
| 1036 | 1039 |
}, |
| 1037 | 1040 |
{
|
| 1038 | 1041 |
.name = "TI UltraSparc II", |
| 1039 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
|
| 1040 |
| (MAXTL << 8)), |
|
| 1042 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
|
| 1041 | 1043 |
.fpu_version = 0x00000000, |
| 1042 | 1044 |
.mmu_version = mmu_us_12, |
| 1043 | 1045 |
.nwindows = 8, |
| 1046 |
.maxtl = 5, |
|
| 1044 | 1047 |
.features = CPU_DEFAULT_FEATURES, |
| 1045 | 1048 |
}, |
| 1046 | 1049 |
{
|
| 1047 | 1050 |
.name = "TI UltraSparc IIi", |
| 1048 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
|
| 1049 |
| (MAXTL << 8)), |
|
| 1051 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
|
| 1050 | 1052 |
.fpu_version = 0x00000000, |
| 1051 | 1053 |
.mmu_version = mmu_us_12, |
| 1052 | 1054 |
.nwindows = 8, |
| 1055 |
.maxtl = 5, |
|
| 1053 | 1056 |
.features = CPU_DEFAULT_FEATURES, |
| 1054 | 1057 |
}, |
| 1055 | 1058 |
{
|
| 1056 | 1059 |
.name = "TI UltraSparc IIe", |
| 1057 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
|
| 1058 |
| (MAXTL << 8)), |
|
| 1060 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
|
| 1059 | 1061 |
.fpu_version = 0x00000000, |
| 1060 | 1062 |
.mmu_version = mmu_us_12, |
| 1061 | 1063 |
.nwindows = 8, |
| 1064 |
.maxtl = 5, |
|
| 1062 | 1065 |
.features = CPU_DEFAULT_FEATURES, |
| 1063 | 1066 |
}, |
| 1064 | 1067 |
{
|
| 1065 | 1068 |
.name = "Sun UltraSparc III", |
| 1066 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
|
| 1067 |
| (MAXTL << 8)), |
|
| 1069 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
|
| 1068 | 1070 |
.fpu_version = 0x00000000, |
| 1069 | 1071 |
.mmu_version = mmu_us_12, |
| 1070 | 1072 |
.nwindows = 8, |
| 1073 |
.maxtl = 5, |
|
| 1071 | 1074 |
.features = CPU_DEFAULT_FEATURES, |
| 1072 | 1075 |
}, |
| 1073 | 1076 |
{
|
| 1074 | 1077 |
.name = "Sun UltraSparc III Cu", |
| 1075 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
|
| 1076 |
| (MAXTL << 8)), |
|
| 1078 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
|
| 1077 | 1079 |
.fpu_version = 0x00000000, |
| 1078 | 1080 |
.mmu_version = mmu_us_3, |
| 1079 | 1081 |
.nwindows = 8, |
| 1082 |
.maxtl = 5, |
|
| 1080 | 1083 |
.features = CPU_DEFAULT_FEATURES, |
| 1081 | 1084 |
}, |
| 1082 | 1085 |
{
|
| 1083 | 1086 |
.name = "Sun UltraSparc IIIi", |
| 1084 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
|
| 1085 |
| (MAXTL << 8)), |
|
| 1087 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
|
| 1086 | 1088 |
.fpu_version = 0x00000000, |
| 1087 | 1089 |
.mmu_version = mmu_us_12, |
| 1088 | 1090 |
.nwindows = 8, |
| 1091 |
.maxtl = 5, |
|
| 1089 | 1092 |
.features = CPU_DEFAULT_FEATURES, |
| 1090 | 1093 |
}, |
| 1091 | 1094 |
{
|
| 1092 | 1095 |
.name = "Sun UltraSparc IV", |
| 1093 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
|
| 1094 |
| (MAXTL << 8)), |
|
| 1096 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
|
| 1095 | 1097 |
.fpu_version = 0x00000000, |
| 1096 | 1098 |
.mmu_version = mmu_us_4, |
| 1097 | 1099 |
.nwindows = 8, |
| 1100 |
.maxtl = 5, |
|
| 1098 | 1101 |
.features = CPU_DEFAULT_FEATURES, |
| 1099 | 1102 |
}, |
| 1100 | 1103 |
{
|
| 1101 | 1104 |
.name = "Sun UltraSparc IV+", |
| 1102 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
|
| 1103 |
| (MAXTL << 8)), |
|
| 1105 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
|
| 1104 | 1106 |
.fpu_version = 0x00000000, |
| 1105 | 1107 |
.mmu_version = mmu_us_12, |
| 1106 | 1108 |
.nwindows = 8, |
| 1109 |
.maxtl = 5, |
|
| 1107 | 1110 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
| 1108 | 1111 |
}, |
| 1109 | 1112 |
{
|
| 1110 | 1113 |
.name = "Sun UltraSparc IIIi+", |
| 1111 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
|
| 1112 |
| (MAXTL << 8)), |
|
| 1114 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
|
| 1113 | 1115 |
.fpu_version = 0x00000000, |
| 1114 | 1116 |
.mmu_version = mmu_us_3, |
| 1115 | 1117 |
.nwindows = 8, |
| 1118 |
.maxtl = 5, |
|
| 1116 | 1119 |
.features = CPU_DEFAULT_FEATURES, |
| 1117 | 1120 |
}, |
| 1118 | 1121 |
{
|
| 1119 | 1122 |
.name = "Sun UltraSparc T1", |
| 1120 | 1123 |
// defined in sparc_ifu_fdp.v and ctu.h |
| 1121 |
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24) |
|
| 1122 |
| (MAXTL << 8)), |
|
| 1124 |
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
|
| 1123 | 1125 |
.fpu_version = 0x00000000, |
| 1124 | 1126 |
.mmu_version = mmu_sun4v, |
| 1125 | 1127 |
.nwindows = 8, |
| 1128 |
.maxtl = 6, |
|
| 1126 | 1129 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
| 1127 | 1130 |
| CPU_FEATURE_GL, |
| 1128 | 1131 |
}, |
| 1129 | 1132 |
{
|
| 1130 | 1133 |
.name = "Sun UltraSparc T2", |
| 1131 | 1134 |
// defined in tlu_asi_ctl.v and n2_revid_cust.v |
| 1132 |
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24) |
|
| 1133 |
| (MAXTL << 8)), |
|
| 1135 |
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
|
| 1134 | 1136 |
.fpu_version = 0x00000000, |
| 1135 | 1137 |
.mmu_version = mmu_sun4v, |
| 1136 | 1138 |
.nwindows = 8, |
| 1139 |
.maxtl = 6, |
|
| 1137 | 1140 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
| 1138 | 1141 |
| CPU_FEATURE_GL, |
| 1139 | 1142 |
}, |
| 1140 | 1143 |
{
|
| 1141 | 1144 |
.name = "NEC UltraSparc I", |
| 1142 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
|
| 1143 |
| (MAXTL << 8)), |
|
| 1145 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
|
| 1144 | 1146 |
.fpu_version = 0x00000000, |
| 1145 | 1147 |
.mmu_version = mmu_us_12, |
| 1146 | 1148 |
.nwindows = 8, |
| 1149 |
.maxtl = 5, |
|
| 1147 | 1150 |
.features = CPU_DEFAULT_FEATURES, |
| 1148 | 1151 |
}, |
| 1149 | 1152 |
#else |
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