Archipelago » qemu

void omap_inth_reset(struct omap_intr_handler_s *s);

qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n);

/* OMAP2 SDRAM controller */

struct omap_sdrc_s;

struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);

# define OMAP24XX_DMA_EXT_DMAREQ5	64

/* omap[123].c */

/* OMAP2 gp timer */

struct omap_gp_timer_s;

struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,

                qemu_irq irq, omap_clk fclk, omap_clk iclk);

void omap_gp_timer_reset(struct omap_gp_timer_s *s);

/* OMAP2 sysctimer */

struct omap_synctimer_s;

struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,

                struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);

void omap_synctimer_reset(struct omap_synctimer_s *s);

struct omap_uart_s;

struct omap_uart_s *omap_uart_init(target_phys_addr_t base,

                qemu_irq irq, omap_clk fclk, omap_clk iclk,

                int chipselect);

void omap_mcspi_reset(struct omap_mcspi_s *s);

struct I2SCodec {

    void *opaque;

                qemu_irq *irq, qemu_irq *dma, omap_clk clk);

void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);

void omap_tap_init(struct omap_target_agent_s *ta,

                struct omap_mpu_state_s *mpu);

/* omap_lcdc.c */

struct omap_lcd_panel_s;

void omap_lcdc_reset(struct omap_lcd_panel_s *s);

    s->it_ena = 1;

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    omap_timer_update(&s->timer);

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    s->timer.ar = 1;

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    s->enh_control = 0x000f;

}

                qemu_irq abort_irq, omap_clk clk)

{

    int iomemtype;

    omap_rtc_tick(s);

}

                qemu_irq *irq, omap_clk clk)

{

    int iomemtype;

    omap_lpg_update(s);

}

{

    int iomemtype;

    struct omap_lpg_s *s = (struct omap_lpg_s *)

    omap_badwidth_write16,

};

                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)

{

    int iomemtype;

    omap_prcm_reset(s);

}

                qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,

                struct omap_mpu_state_s *mpu)

{

    s->padconf[0x44] = 0x00000800;

}

                omap_clk iclk, struct omap_mpu_state_s *mpu)

{

    int iomemtype;