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Name Size
cpu.h 11 kB
gdb-config-dc232b.c 11.8 kB
gdb-config-sample-xtensa-core.c 17.3 kB
helper.c 21.9 kB
helpers.h 997 Bytes
machine.c 1.7 kB
op_helper.c 18.7 kB
translate.c 74.4 kB

Latest revisions

# Date Author Comment
97836cee 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement relocatable vectors

See ISA, 4.4.3 for details.

Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
ccfcaba6 09/10/2011 07:57 pm Max Filippov

target-xtensa: add gdb support

Specific xtensa processor overlay for GDB contains register map in
the gdb/xtensa-config.c. This description is used by the GDB to e.g.
parse 'g' response packets and it may be reused in the qemu's gdbstub
(only XTREG definitions for non-pseudoregisters are needed)....
b67ea0cd 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement memory protection options

- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).

Cache control attribute bits are not used by this implementation.

Signed-off-by: Max Filippov <>...
4dd85b6b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement boolean option

See ISA, 4.3.9

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
47d05a86 09/10/2011 07:57 pm Max Filippov

target-xtensa: add dc232b core and board

This is Diamond 232L Standard Core Rev.B (LE).

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
5b4e481b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement unaligned exception option

See ISA, 4.4.4 for details.

Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
1ddeaa5d 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement SIMCALL

Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.

Note that simcalls that accept buffer addresses expect virtual addresses....
b994e91b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement interrupt option

See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
772177c1 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement accurate window check

See ISA, 4.7.1.3 for details.

Window check is inserted before commands that push "used register
watermark" beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs....
f3df4c04 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement CPENABLE and PRID SRs

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>

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