Revision c227f099 hw/apb_pci.c

b/hw/apb_pci.c
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#define APB_DPRINTF(fmt, ...)
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#endif
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typedef a_target_phys_addr a_pci_addr;
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
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typedef struct APBState {
......
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    PCIHostState host_state;
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} APBState;
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static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
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static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
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                                         uint32_t val)
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{
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    APBState *s = opaque;
......
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}
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static uint32_t pci_apb_config_readl (void *opaque,
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                                            a_target_phys_addr addr)
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                                            target_phys_addr_t addr)
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{
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    APBState *s = opaque;
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    uint32_t val;
......
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    &pci_apb_config_readl,
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};
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static void apb_config_writel (void *opaque, a_target_phys_addr addr,
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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                               uint32_t val)
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{
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    //PCIBus *s = opaque;
......
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}
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static uint32_t apb_config_readl (void *opaque,
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                                  a_target_phys_addr addr)
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                                  target_phys_addr_t addr)
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{
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    //PCIBus *s = opaque;
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    uint32_t val;
......
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    &pci_host_data_readl,
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};
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static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr,
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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                                  uint32_t val)
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{
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    cpu_outb(addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr,
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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                                  uint32_t val)
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{
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    cpu_outw(addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr,
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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                                uint32_t val)
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{
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    cpu_outl(addr & IOPORTS_MASK, val);
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}
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static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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......
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    return val;
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}
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static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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......
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    return val;
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}
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static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr)
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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......
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    qemu_set_irq(pic[irq_num], level);
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}
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PCIBus *pci_apb_init(a_target_phys_addr special_base,
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                     a_target_phys_addr mem_base,
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PCIBus *pci_apb_init(target_phys_addr_t special_base,
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                     target_phys_addr_t mem_base,
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                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
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{
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    DeviceState *dev;

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