Revision c227f099 hw/escc.c
| b/hw/escc.c | ||
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typedef enum {
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chn_a, chn_b, |
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} e_chn_id;
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} chn_id_t;
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#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a') |
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typedef enum {
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ser, kbd, mouse, |
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} e_chn_type;
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} chn_type_t;
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#define SERIO_QUEUE_SIZE 256 |
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qemu_irq irq; |
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uint32_t reg; |
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uint32_t rxint, txint, rxint_under_svc, txint_under_svc; |
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e_chn_id chn; // this channel, A (base+4) or B (base+0)
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e_chn_type type;
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chn_id_t chn; // this channel, A (base+4) or B (base+0)
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chn_type_t type;
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struct ChannelState *otherchn; |
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uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS]; |
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SERIOQueue queue; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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} |
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static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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SerialState *serial = opaque; |
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ChannelState *s; |
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} |
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} |
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static uint32_t escc_mem_readb(void *opaque, a_target_phys_addr addr)
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static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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SerialState *serial = opaque; |
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ChannelState *s; |
| ... | ... | |
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} |
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int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
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int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
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CharDriverState *chrA, CharDriverState *chrB, |
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int clock, int it_shift) |
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{
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put_queue(s, 0); |
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} |
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void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
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void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
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int disabled, int clock, int it_shift) |
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{
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DeviceState *dev; |
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