Revision c227f099 hw/lsi53c895a.c
| b/hw/lsi53c895a.c | ||
|---|---|---|
| 484 | 484 |
static void lsi_do_dma(LSIState *s, int out) |
| 485 | 485 |
{
|
| 486 | 486 |
uint32_t count; |
| 487 |
a_target_phys_addr addr;
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|
| 487 |
target_phys_addr_t addr;
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|
| 488 | 488 |
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| 489 | 489 |
if (!s->current_dma_len) {
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| 490 | 490 |
/* Wait until data is available. */ |
| ... | ... | |
| 1723 | 1723 |
#undef CASE_SET_REG32 |
| 1724 | 1724 |
} |
| 1725 | 1725 |
|
| 1726 |
static void lsi_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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| 1726 |
static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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| 1727 | 1727 |
{
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| 1728 | 1728 |
LSIState *s = opaque; |
| 1729 | 1729 |
|
| 1730 | 1730 |
lsi_reg_writeb(s, addr & 0xff, val); |
| 1731 | 1731 |
} |
| 1732 | 1732 |
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| 1733 |
static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
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| 1733 |
static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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| 1734 | 1734 |
{
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| 1735 | 1735 |
LSIState *s = opaque; |
| 1736 | 1736 |
|
| ... | ... | |
| 1739 | 1739 |
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
| 1740 | 1740 |
} |
| 1741 | 1741 |
|
| 1742 |
static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
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| 1742 |
static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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| 1743 | 1743 |
{
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| 1744 | 1744 |
LSIState *s = opaque; |
| 1745 | 1745 |
|
| ... | ... | |
| 1750 | 1750 |
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); |
| 1751 | 1751 |
} |
| 1752 | 1752 |
|
| 1753 |
static uint32_t lsi_mmio_readb(void *opaque, a_target_phys_addr addr)
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| 1753 |
static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
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| 1754 | 1754 |
{
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| 1755 | 1755 |
LSIState *s = opaque; |
| 1756 | 1756 |
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| 1757 | 1757 |
return lsi_reg_readb(s, addr & 0xff); |
| 1758 | 1758 |
} |
| 1759 | 1759 |
|
| 1760 |
static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr)
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| 1760 |
static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
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| 1761 | 1761 |
{
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| 1762 | 1762 |
LSIState *s = opaque; |
| 1763 | 1763 |
uint32_t val; |
| ... | ... | |
| 1768 | 1768 |
return val; |
| 1769 | 1769 |
} |
| 1770 | 1770 |
|
| 1771 |
static uint32_t lsi_mmio_readl(void *opaque, a_target_phys_addr addr)
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| 1771 |
static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
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| 1772 | 1772 |
{
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| 1773 | 1773 |
LSIState *s = opaque; |
| 1774 | 1774 |
uint32_t val; |
| ... | ... | |
| 1792 | 1792 |
lsi_mmio_writel, |
| 1793 | 1793 |
}; |
| 1794 | 1794 |
|
| 1795 |
static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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| 1795 |
static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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| 1796 | 1796 |
{
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| 1797 | 1797 |
LSIState *s = opaque; |
| 1798 | 1798 |
uint32_t newval; |
| ... | ... | |
| 1806 | 1806 |
s->script_ram[addr >> 2] = newval; |
| 1807 | 1807 |
} |
| 1808 | 1808 |
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| 1809 |
static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
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| 1809 |
static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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| 1810 | 1810 |
{
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| 1811 | 1811 |
LSIState *s = opaque; |
| 1812 | 1812 |
uint32_t newval; |
| ... | ... | |
| 1822 | 1822 |
} |
| 1823 | 1823 |
|
| 1824 | 1824 |
|
| 1825 |
static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
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| 1825 |
static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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| 1826 | 1826 |
{
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| 1827 | 1827 |
LSIState *s = opaque; |
| 1828 | 1828 |
|
| ... | ... | |
| 1830 | 1830 |
s->script_ram[addr >> 2] = val; |
| 1831 | 1831 |
} |
| 1832 | 1832 |
|
| 1833 |
static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr)
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| 1833 |
static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
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| 1834 | 1834 |
{
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| 1835 | 1835 |
LSIState *s = opaque; |
| 1836 | 1836 |
uint32_t val; |
| ... | ... | |
| 1841 | 1841 |
return val & 0xff; |
| 1842 | 1842 |
} |
| 1843 | 1843 |
|
| 1844 |
static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr)
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| 1844 |
static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
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| 1845 | 1845 |
{
|
| 1846 | 1846 |
LSIState *s = opaque; |
| 1847 | 1847 |
uint32_t val; |
| ... | ... | |
| 1853 | 1853 |
return le16_to_cpu(val); |
| 1854 | 1854 |
} |
| 1855 | 1855 |
|
| 1856 |
static uint32_t lsi_ram_readl(void *opaque, a_target_phys_addr addr)
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| 1856 |
static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
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| 1857 | 1857 |
{
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| 1858 | 1858 |
LSIState *s = opaque; |
| 1859 | 1859 |
|
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