Revision c227f099 hw/omap_mmc.c
| b/hw/omap_mmc.c | ||
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| 104 | 104 |
sd_r3, /* OCR register */ |
| 105 | 105 |
sd_r6 = 6, /* Published RCA response */ |
| 106 | 106 |
sd_r1b = -1, |
| 107 |
} e_sd_rsp_type;
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| 107 |
} sd_rsp_type_t;
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| 108 | 108 |
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| 109 | 109 |
static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, |
| 110 |
e_sd_cmd_type type, int busy, e_sd_rsp_type resptype, int init)
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| 110 |
sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
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| 111 | 111 |
{
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| 112 | 112 |
uint32_t rspstatus, mask; |
| 113 | 113 |
int rsplen, timeout; |
| ... | ... | |
| 305 | 305 |
host->clkdiv = 0; |
| 306 | 306 |
} |
| 307 | 307 |
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| 308 |
static uint32_t omap_mmc_read(void *opaque, a_target_phys_addr offset)
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static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
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| 309 | 309 |
{
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| 310 | 310 |
uint16_t i; |
| 311 | 311 |
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
| ... | ... | |
| 394 | 394 |
return 0; |
| 395 | 395 |
} |
| 396 | 396 |
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| 397 |
static void omap_mmc_write(void *opaque, a_target_phys_addr offset,
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static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
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| 398 | 398 |
uint32_t value) |
| 399 | 399 |
{
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| 400 | 400 |
int i; |
| ... | ... | |
| 410 | 410 |
for (i = 0; i < 8; i ++) |
| 411 | 411 |
s->rsp[i] = 0x0000; |
| 412 | 412 |
omap_mmc_command(s, value & 63, (value >> 15) & 1, |
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(e_sd_cmd_type) ((value >> 12) & 3),
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(sd_cmd_type_t) ((value >> 12) & 3),
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| 414 | 414 |
(value >> 11) & 1, |
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(e_sd_rsp_type) ((value >> 8) & 7),
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(sd_rsp_type_t) ((value >> 8) & 7),
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| 416 | 416 |
(value >> 7) & 1); |
| 417 | 417 |
omap_mmc_update(s); |
| 418 | 418 |
break; |
| ... | ... | |
| 569 | 569 |
} |
| 570 | 570 |
} |
| 571 | 571 |
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| 572 |
struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base,
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| 572 |
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
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| 573 | 573 |
BlockDriverState *bd, |
| 574 | 574 |
qemu_irq irq, qemu_irq dma[], omap_clk clk) |
| 575 | 575 |
{
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