Revision c227f099 hw/pflash_cfi02.c
| b/hw/pflash_cfi02.c | ||
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif |
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struct pflash {
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struct pflash_t {
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BlockDriverState *bs; |
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a_target_phys_addr base;
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target_phys_addr_t base;
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uint32_t sector_len; |
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uint32_t chip_len; |
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int mappings; |
| ... | ... | |
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uint8_t cfi_len; |
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uint8_t cfi_table[0x52]; |
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QEMUTimer *timer; |
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a_ram_addr off;
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ram_addr_t off;
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int fl_mem; |
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int rom_mode; |
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void *storage; |
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}; |
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static void pflash_register_memory(a_pflash *pfl, int rom_mode)
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static void pflash_register_memory(pflash_t *pfl, int rom_mode)
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{
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unsigned long phys_offset = pfl->fl_mem; |
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int i; |
| ... | ... | |
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static void pflash_timer (void *opaque) |
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{
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a_pflash *pfl = opaque;
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pflash_t *pfl = opaque;
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */ |
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pfl->cmd = 0; |
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} |
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static uint32_t pflash_read (a_pflash *pfl, uint32_t offset, int width)
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static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
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{
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uint32_t boff; |
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uint32_t ret; |
| ... | ... | |
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} |
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/* update flash content on disk */ |
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static void pflash_update(a_pflash *pfl, int offset,
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static void pflash_update(pflash_t *pfl, int offset,
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int size) |
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{
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int offset_end; |
| ... | ... | |
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} |
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} |
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static void pflash_write (a_pflash *pfl, uint32_t offset, uint32_t value,
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static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
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int width) |
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{
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uint32_t boff; |
| ... | ... | |
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} |
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static uint32_t pflash_readb (void *opaque, a_target_phys_addr addr)
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static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1); |
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} |
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static uint32_t pflash_readw (void *opaque, a_target_phys_addr addr)
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static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
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{
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a_pflash *pfl = opaque;
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 2); |
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} |
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static uint32_t pflash_readl (void *opaque, a_target_phys_addr addr)
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static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
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{
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a_pflash *pfl = opaque;
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 4); |
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} |
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static void pflash_writeb (void *opaque, a_target_phys_addr addr,
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static void pflash_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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pflash_write(opaque, addr, value, 1); |
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} |
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static void pflash_writew (void *opaque, a_target_phys_addr addr,
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static void pflash_writew (void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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a_pflash *pfl = opaque;
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2); |
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} |
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static void pflash_writel (void *opaque, a_target_phys_addr addr,
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static void pflash_writel (void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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a_pflash *pfl = opaque;
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4); |
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} |
| ... | ... | |
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return ret; |
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} |
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a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
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pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
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BlockDriverState *bs, uint32_t sector_len, |
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int nb_blocs, int nb_mappings, int width, |
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uint16_t id0, uint16_t id1, |
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uint16_t id2, uint16_t id3, |
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uint16_t unlock_addr0, uint16_t unlock_addr1) |
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{
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a_pflash *pfl;
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pflash_t *pfl;
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int32_t chip_len; |
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int ret; |
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total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) |
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return NULL; |
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#endif |
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pfl = qemu_mallocz(sizeof(a_pflash));
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pfl = qemu_mallocz(sizeof(pflash_t));
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/* FIXME: Allocate ram ourselves. */ |
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pfl->storage = qemu_get_ram_ptr(off); |
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pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops, |
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