Revision c227f099 hw/ppc405.h
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#include "ppc4xx.h" |
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/* Bootinfo as set-up by u-boot */ |
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typedef struct ppc4xx_bd_info a_ppc4xx_bd_info;
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struct ppc4xx_bd_info {
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typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
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struct ppc4xx_bd_info_t {
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uint32_t bi_memstart; |
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uint32_t bi_memsize; |
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uint32_t bi_flashstart; |
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}; |
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/* PowerPC 405 core */ |
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a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd,
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
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uint32_t flags); |
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CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4],
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a_target_phys_addr ram_sizes[4],
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CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
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target_phys_addr_t ram_sizes[4],
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uint32_t sysclk, qemu_irq **picp, |
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int do_init); |
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CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2],
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a_target_phys_addr ram_sizes[2],
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CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
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target_phys_addr_t ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp, |
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int do_init); |
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/* IBM STBxxx microcontrollers */ |
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CPUState *ppc_stb025_init (a_target_phys_addr ram_bases[2],
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a_target_phys_addr ram_sizes[2],
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CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
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target_phys_addr_t ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp, |
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a_ram_addr *offsetp);
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ram_addr_t *offsetp);
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#endif /* !defined(PPC_405_H) */ |
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