Revision c227f099 hw/ppc405_boards.c
| b/hw/ppc405_boards.c | ||
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| 52 | 52 |
* - NVRAM (0xF0000000) |
| 53 | 53 |
* - FPGA (0xF0300000) |
| 54 | 54 |
*/ |
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typedef struct ref405ep_fpga a_ref405ep_fpga;
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struct ref405ep_fpga {
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typedef struct ref405ep_fpga_t ref405ep_fpga_t;
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struct ref405ep_fpga_t {
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uint8_t reg0; |
| 58 | 58 |
uint8_t reg1; |
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}; |
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static uint32_t ref405ep_fpga_readb (void *opaque, a_target_phys_addr addr)
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static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
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{
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a_ref405ep_fpga *fpga;
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ref405ep_fpga_t *fpga;
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uint32_t ret; |
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fpga = opaque; |
| ... | ... | |
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} |
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static void ref405ep_fpga_writeb (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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a_ref405ep_fpga *fpga;
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ref405ep_fpga_t *fpga;
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fpga = opaque; |
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switch (addr) {
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| ... | ... | |
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} |
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} |
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static uint32_t ref405ep_fpga_readw (void *opaque, a_target_phys_addr addr)
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static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret; |
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|
| ... | ... | |
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} |
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static void ref405ep_fpga_writew (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); |
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} |
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static uint32_t ref405ep_fpga_readl (void *opaque, a_target_phys_addr addr)
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static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret; |
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|
| ... | ... | |
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} |
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static void ref405ep_fpga_writel (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); |
| ... | ... | |
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static void ref405ep_fpga_reset (void *opaque) |
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{
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a_ref405ep_fpga *fpga;
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ref405ep_fpga_t *fpga;
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fpga = opaque; |
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fpga->reg0 = 0x00; |
| ... | ... | |
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static void ref405ep_fpga_init (uint32_t base) |
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{
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a_ref405ep_fpga *fpga;
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ref405ep_fpga_t *fpga;
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int fpga_memory; |
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fpga = qemu_mallocz(sizeof(a_ref405ep_fpga));
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fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
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fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, |
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ref405ep_fpga_write, fpga); |
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cpu_register_physical_memory(base, 0x00000100, fpga_memory); |
| ... | ... | |
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qemu_register_reset(&ref405ep_fpga_reset, fpga); |
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} |
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static void ref405ep_init (a_ram_addr ram_size,
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static void ref405ep_init (ram_addr_t ram_size,
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const char *boot_device, |
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const char *kernel_filename, |
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const char *kernel_cmdline, |
| ... | ... | |
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const char *cpu_model) |
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{
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char *filename; |
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a_ppc4xx_bd_info bd;
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ppc4xx_bd_info_t bd;
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CPUPPCState *env; |
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qemu_irq *pic; |
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a_ram_addr sram_offset, bios_offset, bdloc;
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a_target_phys_addr ram_bases[2], ram_sizes[2];
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ram_addr_t sram_offset, bios_offset, bdloc;
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target_phys_addr_t ram_bases[2], ram_sizes[2];
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target_ulong sram_size, bios_size; |
| 186 | 186 |
//int phy_addr = 0; |
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//static int phy_addr = 1; |
| ... | ... | |
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uint8_t reg1; |
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}; |
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static uint32_t taihu_cpld_readb (void *opaque, a_target_phys_addr addr)
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static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
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{
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taihu_cpld_t *cpld; |
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uint32_t ret; |
| ... | ... | |
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} |
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static void taihu_cpld_writeb (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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taihu_cpld_t *cpld; |
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|
| ... | ... | |
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} |
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} |
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static uint32_t taihu_cpld_readw (void *opaque, a_target_phys_addr addr)
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static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret; |
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|
| ... | ... | |
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} |
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static void taihu_cpld_writew (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); |
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taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); |
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} |
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static uint32_t taihu_cpld_readl (void *opaque, a_target_phys_addr addr)
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static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret; |
| 444 | 444 |
|
| ... | ... | |
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} |
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static void taihu_cpld_writel (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); |
| 457 | 457 |
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); |
| ... | ... | |
| 493 | 493 |
qemu_register_reset(&taihu_cpld_reset, cpld); |
| 494 | 494 |
} |
| 495 | 495 |
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static void taihu_405ep_init(a_ram_addr ram_size,
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static void taihu_405ep_init(ram_addr_t ram_size,
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const char *boot_device, |
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const char *kernel_filename, |
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const char *kernel_cmdline, |
| ... | ... | |
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char *filename; |
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CPUPPCState *env; |
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qemu_irq *pic; |
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a_ram_addr bios_offset;
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a_target_phys_addr ram_bases[2], ram_sizes[2];
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ram_addr_t bios_offset;
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target_phys_addr_t ram_bases[2], ram_sizes[2];
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target_ulong bios_size; |
| 509 | 509 |
target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
| 510 | 510 |
int linux_boot; |
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