Revision c227f099 hw/ppc405_uc.c
b/hw/ppc405_uc.c | ||
---|---|---|
40 | 40 |
#define DEBUG_CLOCKS |
41 | 41 |
//#define DEBUG_CLOCKS_LL |
42 | 42 |
|
43 |
a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd,
|
|
43 |
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
|
|
44 | 44 |
uint32_t flags) |
45 | 45 |
{ |
46 |
a_ram_addr bdloc;
|
|
46 |
ram_addr_t bdloc;
|
|
47 | 47 |
int i, n; |
48 | 48 |
|
49 | 49 |
/* We put the bd structure at the top of memory */ |
50 | 50 |
if (bd->bi_memsize >= 0x01000000UL) |
51 |
bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info); |
|
51 |
bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
|
|
52 | 52 |
else |
53 |
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info); |
|
53 |
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
|
|
54 | 54 |
stl_phys(bdloc + 0x00, bd->bi_memstart); |
55 | 55 |
stl_phys(bdloc + 0x04, bd->bi_memsize); |
56 | 56 |
stl_phys(bdloc + 0x08, bd->bi_flashstart); |
... | ... | |
100 | 100 |
PLB0_ACR = 0x087, |
101 | 101 |
}; |
102 | 102 |
|
103 |
typedef struct ppc4xx_plb a_ppc4xx_plb;
|
|
104 |
struct ppc4xx_plb { |
|
103 |
typedef struct ppc4xx_plb_t ppc4xx_plb_t;
|
|
104 |
struct ppc4xx_plb_t {
|
|
105 | 105 |
uint32_t acr; |
106 | 106 |
uint32_t bear; |
107 | 107 |
uint32_t besr; |
... | ... | |
109 | 109 |
|
110 | 110 |
static target_ulong dcr_read_plb (void *opaque, int dcrn) |
111 | 111 |
{ |
112 |
a_ppc4xx_plb *plb;
|
|
112 |
ppc4xx_plb_t *plb;
|
|
113 | 113 |
target_ulong ret; |
114 | 114 |
|
115 | 115 |
plb = opaque; |
... | ... | |
134 | 134 |
|
135 | 135 |
static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
136 | 136 |
{ |
137 |
a_ppc4xx_plb *plb;
|
|
137 |
ppc4xx_plb_t *plb;
|
|
138 | 138 |
|
139 | 139 |
plb = opaque; |
140 | 140 |
switch (dcrn) { |
... | ... | |
156 | 156 |
|
157 | 157 |
static void ppc4xx_plb_reset (void *opaque) |
158 | 158 |
{ |
159 |
a_ppc4xx_plb *plb;
|
|
159 |
ppc4xx_plb_t *plb;
|
|
160 | 160 |
|
161 | 161 |
plb = opaque; |
162 | 162 |
plb->acr = 0x00000000; |
... | ... | |
166 | 166 |
|
167 | 167 |
static void ppc4xx_plb_init(CPUState *env) |
168 | 168 |
{ |
169 |
a_ppc4xx_plb *plb;
|
|
169 |
ppc4xx_plb_t *plb;
|
|
170 | 170 |
|
171 |
plb = qemu_mallocz(sizeof(a_ppc4xx_plb));
|
|
171 |
plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
|
|
172 | 172 |
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
173 | 173 |
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
174 | 174 |
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
... | ... | |
184 | 184 |
POB0_BEAR = 0x0A4, |
185 | 185 |
}; |
186 | 186 |
|
187 |
typedef struct ppc4xx_pob a_ppc4xx_pob;
|
|
188 |
struct ppc4xx_pob { |
|
187 |
typedef struct ppc4xx_pob_t ppc4xx_pob_t;
|
|
188 |
struct ppc4xx_pob_t {
|
|
189 | 189 |
uint32_t bear; |
190 | 190 |
uint32_t besr[2]; |
191 | 191 |
}; |
192 | 192 |
|
193 | 193 |
static target_ulong dcr_read_pob (void *opaque, int dcrn) |
194 | 194 |
{ |
195 |
a_ppc4xx_pob *pob;
|
|
195 |
ppc4xx_pob_t *pob;
|
|
196 | 196 |
target_ulong ret; |
197 | 197 |
|
198 | 198 |
pob = opaque; |
... | ... | |
215 | 215 |
|
216 | 216 |
static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
217 | 217 |
{ |
218 |
a_ppc4xx_pob *pob;
|
|
218 |
ppc4xx_pob_t *pob;
|
|
219 | 219 |
|
220 | 220 |
pob = opaque; |
221 | 221 |
switch (dcrn) { |
... | ... | |
232 | 232 |
|
233 | 233 |
static void ppc4xx_pob_reset (void *opaque) |
234 | 234 |
{ |
235 |
a_ppc4xx_pob *pob;
|
|
235 |
ppc4xx_pob_t *pob;
|
|
236 | 236 |
|
237 | 237 |
pob = opaque; |
238 | 238 |
/* No error */ |
... | ... | |
243 | 243 |
|
244 | 244 |
static void ppc4xx_pob_init(CPUState *env) |
245 | 245 |
{ |
246 |
a_ppc4xx_pob *pob;
|
|
246 |
ppc4xx_pob_t *pob;
|
|
247 | 247 |
|
248 |
pob = qemu_mallocz(sizeof(a_ppc4xx_pob));
|
|
248 |
pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
|
|
249 | 249 |
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
250 | 250 |
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
251 | 251 |
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
... | ... | |
255 | 255 |
|
256 | 256 |
/*****************************************************************************/ |
257 | 257 |
/* OPB arbitrer */ |
258 |
typedef struct ppc4xx_opba a_ppc4xx_opba;
|
|
259 |
struct ppc4xx_opba { |
|
258 |
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
|
|
259 |
struct ppc4xx_opba_t {
|
|
260 | 260 |
uint8_t cr; |
261 | 261 |
uint8_t pr; |
262 | 262 |
}; |
263 | 263 |
|
264 |
static uint32_t opba_readb (void *opaque, a_target_phys_addr addr)
|
|
264 |
static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
|
|
265 | 265 |
{ |
266 |
a_ppc4xx_opba *opba;
|
|
266 |
ppc4xx_opba_t *opba;
|
|
267 | 267 |
uint32_t ret; |
268 | 268 |
|
269 | 269 |
#ifdef DEBUG_OPBA |
... | ... | |
286 | 286 |
} |
287 | 287 |
|
288 | 288 |
static void opba_writeb (void *opaque, |
289 |
a_target_phys_addr addr, uint32_t value)
|
|
289 |
target_phys_addr_t addr, uint32_t value)
|
|
290 | 290 |
{ |
291 |
a_ppc4xx_opba *opba;
|
|
291 |
ppc4xx_opba_t *opba;
|
|
292 | 292 |
|
293 | 293 |
#ifdef DEBUG_OPBA |
294 | 294 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
307 | 307 |
} |
308 | 308 |
} |
309 | 309 |
|
310 |
static uint32_t opba_readw (void *opaque, a_target_phys_addr addr)
|
|
310 |
static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
|
|
311 | 311 |
{ |
312 | 312 |
uint32_t ret; |
313 | 313 |
|
... | ... | |
321 | 321 |
} |
322 | 322 |
|
323 | 323 |
static void opba_writew (void *opaque, |
324 |
a_target_phys_addr addr, uint32_t value)
|
|
324 |
target_phys_addr_t addr, uint32_t value)
|
|
325 | 325 |
{ |
326 | 326 |
#ifdef DEBUG_OPBA |
327 | 327 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
331 | 331 |
opba_writeb(opaque, addr + 1, value); |
332 | 332 |
} |
333 | 333 |
|
334 |
static uint32_t opba_readl (void *opaque, a_target_phys_addr addr)
|
|
334 |
static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
|
|
335 | 335 |
{ |
336 | 336 |
uint32_t ret; |
337 | 337 |
|
... | ... | |
345 | 345 |
} |
346 | 346 |
|
347 | 347 |
static void opba_writel (void *opaque, |
348 |
a_target_phys_addr addr, uint32_t value)
|
|
348 |
target_phys_addr_t addr, uint32_t value)
|
|
349 | 349 |
{ |
350 | 350 |
#ifdef DEBUG_OPBA |
351 | 351 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
369 | 369 |
|
370 | 370 |
static void ppc4xx_opba_reset (void *opaque) |
371 | 371 |
{ |
372 |
a_ppc4xx_opba *opba;
|
|
372 |
ppc4xx_opba_t *opba;
|
|
373 | 373 |
|
374 | 374 |
opba = opaque; |
375 | 375 |
opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
376 | 376 |
opba->pr = 0x11; |
377 | 377 |
} |
378 | 378 |
|
379 |
static void ppc4xx_opba_init(a_target_phys_addr base)
|
|
379 |
static void ppc4xx_opba_init(target_phys_addr_t base)
|
|
380 | 380 |
{ |
381 |
a_ppc4xx_opba *opba;
|
|
381 |
ppc4xx_opba_t *opba;
|
|
382 | 382 |
int io; |
383 | 383 |
|
384 |
opba = qemu_mallocz(sizeof(a_ppc4xx_opba));
|
|
384 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
|
385 | 385 |
#ifdef DEBUG_OPBA |
386 | 386 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
387 | 387 |
#endif |
... | ... | |
397 | 397 |
|
398 | 398 |
/*****************************************************************************/ |
399 | 399 |
/* Peripheral controller */ |
400 |
typedef struct ppc4xx_ebc a_ppc4xx_ebc;
|
|
401 |
struct ppc4xx_ebc { |
|
400 |
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
|
|
401 |
struct ppc4xx_ebc_t {
|
|
402 | 402 |
uint32_t addr; |
403 | 403 |
uint32_t bcr[8]; |
404 | 404 |
uint32_t bap[8]; |
... | ... | |
415 | 415 |
|
416 | 416 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
417 | 417 |
{ |
418 |
a_ppc4xx_ebc *ebc;
|
|
418 |
ppc4xx_ebc_t *ebc;
|
|
419 | 419 |
target_ulong ret; |
420 | 420 |
|
421 | 421 |
ebc = opaque; |
... | ... | |
499 | 499 |
|
500 | 500 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
501 | 501 |
{ |
502 |
a_ppc4xx_ebc *ebc;
|
|
502 |
ppc4xx_ebc_t *ebc;
|
|
503 | 503 |
|
504 | 504 |
ebc = opaque; |
505 | 505 |
switch (dcrn) { |
... | ... | |
559 | 559 |
|
560 | 560 |
static void ebc_reset (void *opaque) |
561 | 561 |
{ |
562 |
a_ppc4xx_ebc *ebc;
|
|
562 |
ppc4xx_ebc_t *ebc;
|
|
563 | 563 |
int i; |
564 | 564 |
|
565 | 565 |
ebc = opaque; |
... | ... | |
577 | 577 |
|
578 | 578 |
static void ppc405_ebc_init(CPUState *env) |
579 | 579 |
{ |
580 |
a_ppc4xx_ebc *ebc;
|
|
580 |
ppc4xx_ebc_t *ebc;
|
|
581 | 581 |
|
582 |
ebc = qemu_mallocz(sizeof(a_ppc4xx_ebc));
|
|
582 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
|
583 | 583 |
ebc_reset(ebc); |
584 | 584 |
qemu_register_reset(&ebc_reset, ebc); |
585 | 585 |
ppc_dcr_register(env, EBC0_CFGADDR, |
... | ... | |
617 | 617 |
DMA0_POL = 0x126, |
618 | 618 |
}; |
619 | 619 |
|
620 |
typedef struct ppc405_dma a_ppc405_dma;
|
|
621 |
struct ppc405_dma { |
|
620 |
typedef struct ppc405_dma_t ppc405_dma_t;
|
|
621 |
struct ppc405_dma_t {
|
|
622 | 622 |
qemu_irq irqs[4]; |
623 | 623 |
uint32_t cr[4]; |
624 | 624 |
uint32_t ct[4]; |
... | ... | |
633 | 633 |
|
634 | 634 |
static target_ulong dcr_read_dma (void *opaque, int dcrn) |
635 | 635 |
{ |
636 |
a_ppc405_dma *dma;
|
|
636 |
ppc405_dma_t *dma;
|
|
637 | 637 |
|
638 | 638 |
dma = opaque; |
639 | 639 |
|
... | ... | |
642 | 642 |
|
643 | 643 |
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
644 | 644 |
{ |
645 |
a_ppc405_dma *dma;
|
|
645 |
ppc405_dma_t *dma;
|
|
646 | 646 |
|
647 | 647 |
dma = opaque; |
648 | 648 |
} |
649 | 649 |
|
650 | 650 |
static void ppc405_dma_reset (void *opaque) |
651 | 651 |
{ |
652 |
a_ppc405_dma *dma;
|
|
652 |
ppc405_dma_t *dma;
|
|
653 | 653 |
int i; |
654 | 654 |
|
655 | 655 |
dma = opaque; |
... | ... | |
668 | 668 |
|
669 | 669 |
static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) |
670 | 670 |
{ |
671 |
a_ppc405_dma *dma;
|
|
671 |
ppc405_dma_t *dma;
|
|
672 | 672 |
|
673 |
dma = qemu_mallocz(sizeof(a_ppc405_dma));
|
|
673 |
dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
|
674 | 674 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
675 | 675 |
ppc405_dma_reset(dma); |
676 | 676 |
qemu_register_reset(&ppc405_dma_reset, dma); |
... | ... | |
726 | 726 |
|
727 | 727 |
/*****************************************************************************/ |
728 | 728 |
/* GPIO */ |
729 |
typedef struct ppc405_gpio a_ppc405_gpio;
|
|
730 |
struct ppc405_gpio { |
|
729 |
typedef struct ppc405_gpio_t ppc405_gpio_t;
|
|
730 |
struct ppc405_gpio_t {
|
|
731 | 731 |
uint32_t or; |
732 | 732 |
uint32_t tcr; |
733 | 733 |
uint32_t osrh; |
... | ... | |
741 | 741 |
uint32_t isr1l; |
742 | 742 |
}; |
743 | 743 |
|
744 |
static uint32_t ppc405_gpio_readb (void *opaque, a_target_phys_addr addr)
|
|
744 |
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
|
|
745 | 745 |
{ |
746 |
a_ppc405_gpio *gpio;
|
|
746 |
ppc405_gpio_t *gpio;
|
|
747 | 747 |
|
748 | 748 |
gpio = opaque; |
749 | 749 |
#ifdef DEBUG_GPIO |
... | ... | |
754 | 754 |
} |
755 | 755 |
|
756 | 756 |
static void ppc405_gpio_writeb (void *opaque, |
757 |
a_target_phys_addr addr, uint32_t value)
|
|
757 |
target_phys_addr_t addr, uint32_t value)
|
|
758 | 758 |
{ |
759 |
a_ppc405_gpio *gpio;
|
|
759 |
ppc405_gpio_t *gpio;
|
|
760 | 760 |
|
761 | 761 |
gpio = opaque; |
762 | 762 |
#ifdef DEBUG_GPIO |
... | ... | |
765 | 765 |
#endif |
766 | 766 |
} |
767 | 767 |
|
768 |
static uint32_t ppc405_gpio_readw (void *opaque, a_target_phys_addr addr)
|
|
768 |
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
|
|
769 | 769 |
{ |
770 |
a_ppc405_gpio *gpio;
|
|
770 |
ppc405_gpio_t *gpio;
|
|
771 | 771 |
|
772 | 772 |
gpio = opaque; |
773 | 773 |
#ifdef DEBUG_GPIO |
... | ... | |
778 | 778 |
} |
779 | 779 |
|
780 | 780 |
static void ppc405_gpio_writew (void *opaque, |
781 |
a_target_phys_addr addr, uint32_t value)
|
|
781 |
target_phys_addr_t addr, uint32_t value)
|
|
782 | 782 |
{ |
783 |
a_ppc405_gpio *gpio;
|
|
783 |
ppc405_gpio_t *gpio;
|
|
784 | 784 |
|
785 | 785 |
gpio = opaque; |
786 | 786 |
#ifdef DEBUG_GPIO |
... | ... | |
789 | 789 |
#endif |
790 | 790 |
} |
791 | 791 |
|
792 |
static uint32_t ppc405_gpio_readl (void *opaque, a_target_phys_addr addr)
|
|
792 |
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
|
|
793 | 793 |
{ |
794 |
a_ppc405_gpio *gpio;
|
|
794 |
ppc405_gpio_t *gpio;
|
|
795 | 795 |
|
796 | 796 |
gpio = opaque; |
797 | 797 |
#ifdef DEBUG_GPIO |
... | ... | |
802 | 802 |
} |
803 | 803 |
|
804 | 804 |
static void ppc405_gpio_writel (void *opaque, |
805 |
a_target_phys_addr addr, uint32_t value)
|
|
805 |
target_phys_addr_t addr, uint32_t value)
|
|
806 | 806 |
{ |
807 |
a_ppc405_gpio *gpio;
|
|
807 |
ppc405_gpio_t *gpio;
|
|
808 | 808 |
|
809 | 809 |
gpio = opaque; |
810 | 810 |
#ifdef DEBUG_GPIO |
... | ... | |
827 | 827 |
|
828 | 828 |
static void ppc405_gpio_reset (void *opaque) |
829 | 829 |
{ |
830 |
a_ppc405_gpio *gpio;
|
|
830 |
ppc405_gpio_t *gpio;
|
|
831 | 831 |
|
832 | 832 |
gpio = opaque; |
833 | 833 |
} |
834 | 834 |
|
835 |
static void ppc405_gpio_init(a_target_phys_addr base)
|
|
835 |
static void ppc405_gpio_init(target_phys_addr_t base)
|
|
836 | 836 |
{ |
837 |
a_ppc405_gpio *gpio;
|
|
837 |
ppc405_gpio_t *gpio;
|
|
838 | 838 |
int io; |
839 | 839 |
|
840 |
gpio = qemu_mallocz(sizeof(a_ppc405_gpio));
|
|
840 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
|
841 | 841 |
#ifdef DEBUG_GPIO |
842 | 842 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
843 | 843 |
#endif |
... | ... | |
856 | 856 |
OCM0_DSACNTL = 0x01B, |
857 | 857 |
}; |
858 | 858 |
|
859 |
typedef struct ppc405_ocm a_ppc405_ocm;
|
|
860 |
struct ppc405_ocm { |
|
859 |
typedef struct ppc405_ocm_t ppc405_ocm_t;
|
|
860 |
struct ppc405_ocm_t {
|
|
861 | 861 |
target_ulong offset; |
862 | 862 |
uint32_t isarc; |
863 | 863 |
uint32_t isacntl; |
... | ... | |
865 | 865 |
uint32_t dsacntl; |
866 | 866 |
}; |
867 | 867 |
|
868 |
static void ocm_update_mappings (a_ppc405_ocm *ocm,
|
|
868 |
static void ocm_update_mappings (ppc405_ocm_t *ocm,
|
|
869 | 869 |
uint32_t isarc, uint32_t isacntl, |
870 | 870 |
uint32_t dsarc, uint32_t dsacntl) |
871 | 871 |
{ |
... | ... | |
922 | 922 |
|
923 | 923 |
static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
924 | 924 |
{ |
925 |
a_ppc405_ocm *ocm;
|
|
925 |
ppc405_ocm_t *ocm;
|
|
926 | 926 |
target_ulong ret; |
927 | 927 |
|
928 | 928 |
ocm = opaque; |
... | ... | |
949 | 949 |
|
950 | 950 |
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
951 | 951 |
{ |
952 |
a_ppc405_ocm *ocm;
|
|
952 |
ppc405_ocm_t *ocm;
|
|
953 | 953 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
954 | 954 |
|
955 | 955 |
ocm = opaque; |
... | ... | |
980 | 980 |
|
981 | 981 |
static void ocm_reset (void *opaque) |
982 | 982 |
{ |
983 |
a_ppc405_ocm *ocm;
|
|
983 |
ppc405_ocm_t *ocm;
|
|
984 | 984 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
985 | 985 |
|
986 | 986 |
ocm = opaque; |
... | ... | |
997 | 997 |
|
998 | 998 |
static void ppc405_ocm_init(CPUState *env) |
999 | 999 |
{ |
1000 |
a_ppc405_ocm *ocm;
|
|
1000 |
ppc405_ocm_t *ocm;
|
|
1001 | 1001 |
|
1002 |
ocm = qemu_mallocz(sizeof(a_ppc405_ocm));
|
|
1002 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
|
1003 | 1003 |
ocm->offset = qemu_ram_alloc(4096); |
1004 | 1004 |
ocm_reset(ocm); |
1005 | 1005 |
qemu_register_reset(&ocm_reset, ocm); |
... | ... | |
1015 | 1015 |
|
1016 | 1016 |
/*****************************************************************************/ |
1017 | 1017 |
/* I2C controller */ |
1018 |
typedef struct ppc4xx_i2c a_ppc4xx_i2c;
|
|
1019 |
struct ppc4xx_i2c { |
|
1018 |
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
|
|
1019 |
struct ppc4xx_i2c_t {
|
|
1020 | 1020 |
qemu_irq irq; |
1021 | 1021 |
uint8_t mdata; |
1022 | 1022 |
uint8_t lmadr; |
... | ... | |
1035 | 1035 |
uint8_t directcntl; |
1036 | 1036 |
}; |
1037 | 1037 |
|
1038 |
static uint32_t ppc4xx_i2c_readb (void *opaque, a_target_phys_addr addr)
|
|
1038 |
static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
|
|
1039 | 1039 |
{ |
1040 |
a_ppc4xx_i2c *i2c;
|
|
1040 |
ppc4xx_i2c_t *i2c;
|
|
1041 | 1041 |
uint32_t ret; |
1042 | 1042 |
|
1043 | 1043 |
#ifdef DEBUG_I2C |
... | ... | |
1103 | 1103 |
} |
1104 | 1104 |
|
1105 | 1105 |
static void ppc4xx_i2c_writeb (void *opaque, |
1106 |
a_target_phys_addr addr, uint32_t value)
|
|
1106 |
target_phys_addr_t addr, uint32_t value)
|
|
1107 | 1107 |
{ |
1108 |
a_ppc4xx_i2c *i2c;
|
|
1108 |
ppc4xx_i2c_t *i2c;
|
|
1109 | 1109 |
|
1110 | 1110 |
#ifdef DEBUG_I2C |
1111 | 1111 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
1162 | 1162 |
} |
1163 | 1163 |
} |
1164 | 1164 |
|
1165 |
static uint32_t ppc4xx_i2c_readw (void *opaque, a_target_phys_addr addr)
|
|
1165 |
static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
|
|
1166 | 1166 |
{ |
1167 | 1167 |
uint32_t ret; |
1168 | 1168 |
|
... | ... | |
1176 | 1176 |
} |
1177 | 1177 |
|
1178 | 1178 |
static void ppc4xx_i2c_writew (void *opaque, |
1179 |
a_target_phys_addr addr, uint32_t value)
|
|
1179 |
target_phys_addr_t addr, uint32_t value)
|
|
1180 | 1180 |
{ |
1181 | 1181 |
#ifdef DEBUG_I2C |
1182 | 1182 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
1186 | 1186 |
ppc4xx_i2c_writeb(opaque, addr + 1, value); |
1187 | 1187 |
} |
1188 | 1188 |
|
1189 |
static uint32_t ppc4xx_i2c_readl (void *opaque, a_target_phys_addr addr)
|
|
1189 |
static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
|
|
1190 | 1190 |
{ |
1191 | 1191 |
uint32_t ret; |
1192 | 1192 |
|
... | ... | |
1202 | 1202 |
} |
1203 | 1203 |
|
1204 | 1204 |
static void ppc4xx_i2c_writel (void *opaque, |
1205 |
a_target_phys_addr addr, uint32_t value)
|
|
1205 |
target_phys_addr_t addr, uint32_t value)
|
|
1206 | 1206 |
{ |
1207 | 1207 |
#ifdef DEBUG_I2C |
1208 | 1208 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
1228 | 1228 |
|
1229 | 1229 |
static void ppc4xx_i2c_reset (void *opaque) |
1230 | 1230 |
{ |
1231 |
a_ppc4xx_i2c *i2c;
|
|
1231 |
ppc4xx_i2c_t *i2c;
|
|
1232 | 1232 |
|
1233 | 1233 |
i2c = opaque; |
1234 | 1234 |
i2c->mdata = 0x00; |
... | ... | |
1242 | 1242 |
i2c->directcntl = 0x0F; |
1243 | 1243 |
} |
1244 | 1244 |
|
1245 |
static void ppc405_i2c_init(a_target_phys_addr base, qemu_irq irq)
|
|
1245 |
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
|
|
1246 | 1246 |
{ |
1247 |
a_ppc4xx_i2c *i2c;
|
|
1247 |
ppc4xx_i2c_t *i2c;
|
|
1248 | 1248 |
int io; |
1249 | 1249 |
|
1250 |
i2c = qemu_mallocz(sizeof(a_ppc4xx_i2c));
|
|
1250 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
|
1251 | 1251 |
i2c->irq = irq; |
1252 | 1252 |
#ifdef DEBUG_I2C |
1253 | 1253 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
... | ... | |
1260 | 1260 |
|
1261 | 1261 |
/*****************************************************************************/ |
1262 | 1262 |
/* General purpose timers */ |
1263 |
typedef struct ppc4xx_gpt a_ppc4xx_gpt;
|
|
1264 |
struct ppc4xx_gpt { |
|
1263 |
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
|
|
1264 |
struct ppc4xx_gpt_t {
|
|
1265 | 1265 |
int64_t tb_offset; |
1266 | 1266 |
uint32_t tb_freq; |
1267 | 1267 |
struct QEMUTimer *timer; |
... | ... | |
1275 | 1275 |
uint32_t mask[5]; |
1276 | 1276 |
}; |
1277 | 1277 |
|
1278 |
static uint32_t ppc4xx_gpt_readb (void *opaque, a_target_phys_addr addr)
|
|
1278 |
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
|
|
1279 | 1279 |
{ |
1280 | 1280 |
#ifdef DEBUG_GPT |
1281 | 1281 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
... | ... | |
1285 | 1285 |
} |
1286 | 1286 |
|
1287 | 1287 |
static void ppc4xx_gpt_writeb (void *opaque, |
1288 |
a_target_phys_addr addr, uint32_t value)
|
|
1288 |
target_phys_addr_t addr, uint32_t value)
|
|
1289 | 1289 |
{ |
1290 | 1290 |
#ifdef DEBUG_I2C |
1291 | 1291 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
1294 | 1294 |
/* XXX: generate a bus fault */ |
1295 | 1295 |
} |
1296 | 1296 |
|
1297 |
static uint32_t ppc4xx_gpt_readw (void *opaque, a_target_phys_addr addr)
|
|
1297 |
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
|
|
1298 | 1298 |
{ |
1299 | 1299 |
#ifdef DEBUG_GPT |
1300 | 1300 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
... | ... | |
1304 | 1304 |
} |
1305 | 1305 |
|
1306 | 1306 |
static void ppc4xx_gpt_writew (void *opaque, |
1307 |
a_target_phys_addr addr, uint32_t value)
|
|
1307 |
target_phys_addr_t addr, uint32_t value)
|
|
1308 | 1308 |
{ |
1309 | 1309 |
#ifdef DEBUG_I2C |
1310 | 1310 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
... | ... | |
1313 | 1313 |
/* XXX: generate a bus fault */ |
1314 | 1314 |
} |
1315 | 1315 |
|
1316 |
static int ppc4xx_gpt_compare (a_ppc4xx_gpt *gpt, int n)
|
|
1316 |
static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
|
|
1317 | 1317 |
{ |
1318 | 1318 |
/* XXX: TODO */ |
1319 | 1319 |
return 0; |
1320 | 1320 |
} |
1321 | 1321 |
|
1322 |
static void ppc4xx_gpt_set_output (a_ppc4xx_gpt *gpt, int n, int level)
|
|
1322 |
static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
|
|
1323 | 1323 |
{ |
1324 | 1324 |
/* XXX: TODO */ |
1325 | 1325 |
} |
1326 | 1326 |
|
1327 |
static void ppc4xx_gpt_set_outputs (a_ppc4xx_gpt *gpt)
|
|
1327 |
static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
|
|
1328 | 1328 |
{ |
1329 | 1329 |
uint32_t mask; |
1330 | 1330 |
int i; |
... | ... | |
1345 | 1345 |
} |
1346 | 1346 |
} |
1347 | 1347 |
|
1348 |
static void ppc4xx_gpt_set_irqs (a_ppc4xx_gpt *gpt)
|
|
1348 |
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
|
|
1349 | 1349 |
{ |
1350 | 1350 |
uint32_t mask; |
1351 | 1351 |
int i; |
... | ... | |
1360 | 1360 |
} |
1361 | 1361 |
} |
1362 | 1362 |
|
1363 |
static void ppc4xx_gpt_compute_timer (a_ppc4xx_gpt *gpt)
|
|
1363 |
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
|
|
1364 | 1364 |
{ |
1365 | 1365 |
/* XXX: TODO */ |
1366 | 1366 |
} |
1367 | 1367 |
|
1368 |
static uint32_t ppc4xx_gpt_readl (void *opaque, a_target_phys_addr addr)
|
|
1368 |
static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
|
|
1369 | 1369 |
{ |
1370 |
a_ppc4xx_gpt *gpt;
|
|
1370 |
ppc4xx_gpt_t *gpt;
|
|
1371 | 1371 |
uint32_t ret; |
1372 | 1372 |
int idx; |
1373 | 1373 |
|
... | ... | |
1421 | 1421 |
} |
1422 | 1422 |
|
1423 | 1423 |
static void ppc4xx_gpt_writel (void *opaque, |
1424 |
a_target_phys_addr addr, uint32_t value)
|
|
1424 |
target_phys_addr_t addr, uint32_t value)
|
|
1425 | 1425 |
{ |
1426 |
a_ppc4xx_gpt *gpt;
|
|
1426 |
ppc4xx_gpt_t *gpt;
|
|
1427 | 1427 |
int idx; |
1428 | 1428 |
|
1429 | 1429 |
#ifdef DEBUG_I2C |
... | ... | |
1496 | 1496 |
|
1497 | 1497 |
static void ppc4xx_gpt_cb (void *opaque) |
1498 | 1498 |
{ |
1499 |
a_ppc4xx_gpt *gpt;
|
|
1499 |
ppc4xx_gpt_t *gpt;
|
|
1500 | 1500 |
|
1501 | 1501 |
gpt = opaque; |
1502 | 1502 |
ppc4xx_gpt_set_irqs(gpt); |
... | ... | |
1506 | 1506 |
|
1507 | 1507 |
static void ppc4xx_gpt_reset (void *opaque) |
1508 | 1508 |
{ |
1509 |
a_ppc4xx_gpt *gpt;
|
|
1509 |
ppc4xx_gpt_t *gpt;
|
|
1510 | 1510 |
int i; |
1511 | 1511 |
|
1512 | 1512 |
gpt = opaque; |
... | ... | |
1522 | 1522 |
} |
1523 | 1523 |
} |
1524 | 1524 |
|
1525 |
static void ppc4xx_gpt_init(a_target_phys_addr base, qemu_irq irqs[5])
|
|
1525 |
static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
|
|
1526 | 1526 |
{ |
1527 |
a_ppc4xx_gpt *gpt;
|
|
1527 |
ppc4xx_gpt_t *gpt;
|
|
1528 | 1528 |
int i; |
1529 | 1529 |
int io; |
1530 | 1530 |
|
1531 |
gpt = qemu_mallocz(sizeof(a_ppc4xx_gpt));
|
|
1531 |
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
|
1532 | 1532 |
for (i = 0; i < 5; i++) { |
1533 | 1533 |
gpt->irqs[i] = irqs[i]; |
1534 | 1534 |
} |
... | ... | |
1566 | 1566 |
MAL0_RCBS1 = 0x1E1, |
1567 | 1567 |
}; |
1568 | 1568 |
|
1569 |
typedef struct ppc40x_mal a_ppc40x_mal;
|
|
1570 |
struct ppc40x_mal { |
|
1569 |
typedef struct ppc40x_mal_t ppc40x_mal_t;
|
|
1570 |
struct ppc40x_mal_t {
|
|
1571 | 1571 |
qemu_irq irqs[4]; |
1572 | 1572 |
uint32_t cfg; |
1573 | 1573 |
uint32_t esr; |
... | ... | |
1589 | 1589 |
|
1590 | 1590 |
static target_ulong dcr_read_mal (void *opaque, int dcrn) |
1591 | 1591 |
{ |
1592 |
a_ppc40x_mal *mal;
|
|
1592 |
ppc40x_mal_t *mal;
|
|
1593 | 1593 |
target_ulong ret; |
1594 | 1594 |
|
1595 | 1595 |
mal = opaque; |
... | ... | |
1661 | 1661 |
|
1662 | 1662 |
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
1663 | 1663 |
{ |
1664 |
a_ppc40x_mal *mal;
|
|
1664 |
ppc40x_mal_t *mal;
|
|
1665 | 1665 |
int idx; |
1666 | 1666 |
|
1667 | 1667 |
mal = opaque; |
... | ... | |
1741 | 1741 |
|
1742 | 1742 |
static void ppc40x_mal_reset (void *opaque) |
1743 | 1743 |
{ |
1744 |
a_ppc40x_mal *mal;
|
|
1744 |
ppc40x_mal_t *mal;
|
|
1745 | 1745 |
|
1746 | 1746 |
mal = opaque; |
1747 | 1747 |
mal->cfg = 0x0007C000; |
... | ... | |
1757 | 1757 |
|
1758 | 1758 |
static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) |
1759 | 1759 |
{ |
1760 |
a_ppc40x_mal *mal;
|
|
1760 |
ppc40x_mal_t *mal;
|
|
1761 | 1761 |
int i; |
1762 | 1762 |
|
1763 |
mal = qemu_mallocz(sizeof(a_ppc40x_mal));
|
|
1763 |
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
|
1764 | 1764 |
for (i = 0; i < 4; i++) |
1765 | 1765 |
mal->irqs[i] = irqs[i]; |
1766 | 1766 |
ppc40x_mal_reset(mal); |
... | ... | |
1895 | 1895 |
PPC405CR_CLK_NB = 7, |
1896 | 1896 |
}; |
1897 | 1897 |
|
1898 |
typedef struct ppc405cr_cpc a_ppc405cr_cpc;
|
|
1899 |
struct ppc405cr_cpc { |
|
1900 |
a_clk_setup clk_setup[PPC405CR_CLK_NB];
|
|
1898 |
typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
|
|
1899 |
struct ppc405cr_cpc_t {
|
|
1900 |
clk_setup_t clk_setup[PPC405CR_CLK_NB];
|
|
1901 | 1901 |
uint32_t sysclk; |
1902 | 1902 |
uint32_t psr; |
1903 | 1903 |
uint32_t cr0; |
... | ... | |
1908 | 1908 |
uint32_t fr; |
1909 | 1909 |
}; |
1910 | 1910 |
|
1911 |
static void ppc405cr_clk_setup (a_ppc405cr_cpc *cpc)
|
|
1911 |
static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
|
|
1912 | 1912 |
{ |
1913 | 1913 |
uint64_t VCO_out, PLL_out; |
1914 | 1914 |
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
... | ... | |
1963 | 1963 |
|
1964 | 1964 |
static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
1965 | 1965 |
{ |
1966 |
a_ppc405cr_cpc *cpc;
|
|
1966 |
ppc405cr_cpc_t *cpc;
|
|
1967 | 1967 |
target_ulong ret; |
1968 | 1968 |
|
1969 | 1969 |
cpc = opaque; |
... | ... | |
2003 | 2003 |
|
2004 | 2004 |
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
2005 | 2005 |
{ |
2006 |
a_ppc405cr_cpc *cpc;
|
|
2006 |
ppc405cr_cpc_t *cpc;
|
|
2007 | 2007 |
|
2008 | 2008 |
cpc = opaque; |
2009 | 2009 |
switch (dcrn) { |
... | ... | |
2036 | 2036 |
|
2037 | 2037 |
static void ppc405cr_cpc_reset (void *opaque) |
2038 | 2038 |
{ |
2039 |
a_ppc405cr_cpc *cpc;
|
|
2039 |
ppc405cr_cpc_t *cpc;
|
|
2040 | 2040 |
int D; |
2041 | 2041 |
|
2042 | 2042 |
cpc = opaque; |
... | ... | |
2095 | 2095 |
ppc405cr_clk_setup(cpc); |
2096 | 2096 |
} |
2097 | 2097 |
|
2098 |
static void ppc405cr_clk_init (a_ppc405cr_cpc *cpc)
|
|
2098 |
static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
|
|
2099 | 2099 |
{ |
2100 | 2100 |
int D; |
2101 | 2101 |
|
... | ... | |
2121 | 2121 |
cpc->psr |= D << 17; |
2122 | 2122 |
} |
2123 | 2123 |
|
2124 |
static void ppc405cr_cpc_init (CPUState *env, a_clk_setup clk_setup[7],
|
|
2124 |
static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
|
|
2125 | 2125 |
uint32_t sysclk) |
2126 | 2126 |
{ |
2127 |
a_ppc405cr_cpc *cpc;
|
|
2127 |
ppc405cr_cpc_t *cpc;
|
|
2128 | 2128 |
|
2129 |
cpc = qemu_mallocz(sizeof(a_ppc405cr_cpc));
|
|
2129 |
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
|
2130 | 2130 |
memcpy(cpc->clk_setup, clk_setup, |
2131 |
PPC405CR_CLK_NB * sizeof(a_clk_setup));
|
|
2131 |
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
|
2132 | 2132 |
cpc->sysclk = sysclk; |
2133 | 2133 |
cpc->jtagid = 0x42051049; |
2134 | 2134 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
... | ... | |
2152 | 2152 |
ppc405cr_cpc_reset(cpc); |
2153 | 2153 |
} |
2154 | 2154 |
|
2155 |
CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4],
|
|
2156 |
a_target_phys_addr ram_sizes[4],
|
|
2155 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
|
2156 |
target_phys_addr_t ram_sizes[4],
|
|
2157 | 2157 |
uint32_t sysclk, qemu_irq **picp, |
2158 | 2158 |
int do_init) |
2159 | 2159 |
{ |
2160 |
a_clk_setup clk_setup[PPC405CR_CLK_NB];
|
|
2160 |
clk_setup_t clk_setup[PPC405CR_CLK_NB];
|
|
2161 | 2161 |
qemu_irq dma_irqs[4]; |
2162 | 2162 |
CPUState *env; |
2163 | 2163 |
qemu_irq *pic, *irqs; |
... | ... | |
2240 | 2240 |
PPC405EP_CLK_NB = 8, |
2241 | 2241 |
}; |
2242 | 2242 |
|
2243 |
typedef struct ppc405ep_cpc a_ppc405ep_cpc;
|
|
2244 |
struct ppc405ep_cpc { |
|
2243 |
typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
|
|
2244 |
struct ppc405ep_cpc_t {
|
|
2245 | 2245 |
uint32_t sysclk; |
2246 |
a_clk_setup clk_setup[PPC405EP_CLK_NB];
|
|
2246 |
clk_setup_t clk_setup[PPC405EP_CLK_NB];
|
|
2247 | 2247 |
uint32_t boot; |
2248 | 2248 |
uint32_t epctl; |
2249 | 2249 |
uint32_t pllmr[2]; |
... | ... | |
2257 | 2257 |
uint32_t sr; |
2258 | 2258 |
}; |
2259 | 2259 |
|
2260 |
static void ppc405ep_compute_clocks (a_ppc405ep_cpc *cpc)
|
|
2260 |
static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
|
|
2261 | 2261 |
{ |
2262 | 2262 |
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
2263 | 2263 |
uint32_t UART0_clk, UART1_clk; |
... | ... | |
2366 | 2366 |
|
2367 | 2367 |
static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
2368 | 2368 |
{ |
2369 |
a_ppc405ep_cpc *cpc;
|
|
2369 |
ppc405ep_cpc_t *cpc;
|
|
2370 | 2370 |
target_ulong ret; |
2371 | 2371 |
|
2372 | 2372 |
cpc = opaque; |
... | ... | |
2406 | 2406 |
|
2407 | 2407 |
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
2408 | 2408 |
{ |
2409 |
a_ppc405ep_cpc *cpc;
|
|
2409 |
ppc405ep_cpc_t *cpc;
|
|
2410 | 2410 |
|
2411 | 2411 |
cpc = opaque; |
2412 | 2412 |
switch (dcrn) { |
... | ... | |
2443 | 2443 |
|
2444 | 2444 |
static void ppc405ep_cpc_reset (void *opaque) |
2445 | 2445 |
{ |
2446 |
a_ppc405ep_cpc *cpc = opaque;
|
|
2446 |
ppc405ep_cpc_t *cpc = opaque;
|
|
2447 | 2447 |
|
2448 | 2448 |
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
2449 | 2449 |
cpc->epctl = 0x00000000; |
... | ... | |
2459 | 2459 |
} |
2460 | 2460 |
|
2461 | 2461 |
/* XXX: sysclk should be between 25 and 100 MHz */ |
2462 |
static void ppc405ep_cpc_init (CPUState *env, a_clk_setup clk_setup[8],
|
|
2462 |
static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
|
|
2463 | 2463 |
uint32_t sysclk) |
2464 | 2464 |
{ |
2465 |
a_ppc405ep_cpc *cpc;
|
|
2465 |
ppc405ep_cpc_t *cpc;
|
|
2466 | 2466 |
|
2467 |
cpc = qemu_mallocz(sizeof(a_ppc405ep_cpc));
|
|
2467 |
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
|
2468 | 2468 |
memcpy(cpc->clk_setup, clk_setup, |
2469 |
PPC405EP_CLK_NB * sizeof(a_clk_setup));
|
|
2469 |
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
|
2470 | 2470 |
cpc->jtagid = 0x20267049; |
2471 | 2471 |
cpc->sysclk = sysclk; |
2472 | 2472 |
ppc405ep_cpc_reset(cpc); |
... | ... | |
2497 | 2497 |
#endif |
2498 | 2498 |
} |
2499 | 2499 |
|
2500 |
CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2],
|
|
2501 |
a_target_phys_addr ram_sizes[2],
|
|
2500 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
|
2501 |
target_phys_addr_t ram_sizes[2],
|
|
2502 | 2502 |
uint32_t sysclk, qemu_irq **picp, |
2503 | 2503 |
int do_init) |
2504 | 2504 |
{ |
2505 |
a_clk_setup clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
|
|
2505 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
|
|
2506 | 2506 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2507 | 2507 |
CPUState *env; |
2508 | 2508 |
qemu_irq *pic, *irqs; |
Also available in: Unified diff