Revision c227f099 hw/ppc4xx_pci.c
b/hw/ppc4xx_pci.c | ||
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#include "ppc.h" |
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#include "ppc4xx.h" |
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typedef a_target_phys_addr a_pci_addr;
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typedef target_phys_addr_t pci_addr_t;
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#include "pci.h" |
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#include "pci_host.h" |
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#include "bswap.h" |
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#define PCI_REG_SIZE 0x40 |
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static uint32_t pci4xx_cfgaddr_readl(void *opaque, a_target_phys_addr addr)
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static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
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{ |
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PPC4xxPCIState *ppc4xx_pci = opaque; |
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&pci4xx_cfgaddr_readl, |
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}; |
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static void pci4xx_cfgaddr_writel(void *opaque, a_target_phys_addr addr,
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static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{ |
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PPC4xxPCIState *ppc4xx_pci = opaque; |
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&pci_host_data_writel, |
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}; |
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static void ppc4xx_pci_reg_write4(void *opaque, a_target_phys_addr offset,
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static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
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uint32_t value) |
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{ |
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struct PPC4xxPCIState *pci = opaque; |
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} |
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} |
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static uint32_t ppc4xx_pci_reg_read4(void *opaque, a_target_phys_addr offset)
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static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
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{ |
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struct PPC4xxPCIState *pci = opaque; |
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uint32_t value; |
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/* XXX Interrupt acknowledge cycles not supported. */ |
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PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], |
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a_target_phys_addr config_space,
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a_target_phys_addr int_ack,
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a_target_phys_addr special_cycle,
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a_target_phys_addr registers)
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers)
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{ |
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PPC4xxPCIState *controller; |
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int index; |
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